7S265 Search Results

sn7513b

Contextual Info: • 0 ^ 1 7 2 4 0üô25bl 1 ■ T i m TEXAS INSTR LIN/INTFC T S 2 _ ^ \ V SN75136 QUADRUPLE BUS TRANSCEIVER WITH 3-STATE OUTPUTS 4QE D D2291, J A N U A R Y 1 9 7 7 -R E V IS E D SEPTEMBER 1986 • P-N-P Inputs for Minim al Input Loading D, J . O R N P A C K A G E

2SC 2320

Abstract: SCAS04QA-P3110
Contextual Info: 54ACT11253,74ACT11253 DUAL 1-0F-4 DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS SCAS040A - D3110, MARCH 1988 - REVISED APRIL 1993 * Inputs Are TTL-Voltage Compatible 54ACT11253 . . . J PACKAGE 74ACT11253 . . . D OH N PACKAGE TOP VIEW * 3-State Version of'ACT11153

1sv 134

Contextual Info: 54ACT11640, 74ACT11640 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCAS027A - D2957, JULY 1987 - REVISED APRIL 1993 54ACT11640. . . JT PACKAGE 74ACT11640 . . . DW OR NT PACKAGE TOP VIEW B idirectional Bus Transceivers In H ig h-D ensity 24-P in Packages

L78015

Contextual Info: TL780 SERIES POSITIVE VOLTAGE REGULATORS SLVS055B - APRIL 1981 - REVISED AUGUST 1995 • ±1% Output Tolerance at 25°C • +2% Output Tolerance Over Full Operating Range • Thermal Shutdown • Internal Short-Circuit Current Limiting • Pinout Identical to |jA7800 Series

Contextual Info: SN55ALS192, SN75ALS192 QUADRUPLE DIFFERENTIAL LINE DRIVERS SLLS007C - JULY 1985 - REVISED MAY 1995 Meets or Exceeds the Requirements of ANSI Standard EIA/TIA-422-B and ITU Recommendation V.11 SN55ALS192. . . J OR W PACKAGE SN75ALS19 2 . D OR N PACKAGE TOP VIEW

Contextual Info: SN54ALS1244A, SN74ALS1244A OCTAL BUFFERS AND DRIVERS WITH 3-STATE OUTPUTS SD A S1B 6B-JU LY 1990-R E V IS E D JANUARY 1995 Low-Power Versions of 'ALS244 Series 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers pnp Inputs Reduce dc Loading

S1818

Abstract: 74AS181B
Contextual Info: PRODUCT PREVIEW SN54AS181B, SN74AS181B ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS D 2661, DECEM BER 1 9 8 5 - REVISED M AY 1986 S N 5 4 A S 1 8 1 B . . . J T OR J W P A C K A G E S N 7 4 A S 1 8 1 B . . . N OR NT P A C K A G E P a c k a g e O p tio n s In clu d e C o m p a c t 3 0 0 -m il

74278

Contextual Info: TYPES SN54278, SN74278 4-BIT CASCADABLE PRIORITY REGISTERS M AY 1 972 —R E V ISE D A P R IL 1 98 5 Latched Data Inputs Serve as Buffer Register and Can also: Synchronize Data Acquisition "Debounce" Mechanical Switch Input • Cascading Input PO and Output P1

D3318

Contextual Info: 74AC11139 DUAL 2-LINE TO 4-LINE DECODER/DEMULTIPLEXER D3318, JULY 1989 - R EV ISED APRIL 1993 * Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems * Incorporates Two Enable Inputs to Simplify Cascading and/or Data Reception

Contextual Info: SN74ACT7881 1024 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS227C - FEBRUARY 1993 - REVISED FEBRUARY 1996 • Member of the Texas Instruments Wldebus Family • Independent Asynchronous Inputs and Outputs • Input-Ready, Output-Ready, and Half-Full Flags

DA 2688

Abstract: transistor DA 2688 LT 5265 transistor mj 3055 c2688 C-2688 equivalent transistor TIP3055 c2688 L c2688 transistor tRANSISTOR c2688
Contextual Info: TEXAS r ÌNSTR 8961726 TEXAS IN STR 62C OPTO 37004 TIP3055 N-P-N SILICON POWER TRANSISTOR T - 3 3 DECEMBER 1970 - REVISED OCTOBER 1884 Designed for Complementary Use with TIP2955 9 0 W at 2 5 ° C C ase T emperature 15 A Continuous Collector Current Plastic-Case Version of 2N 3055

Contextual Info: TYPES SN54ALS677, SN54ALS678. SN74ALS677, SN74ALS678 ADDRESS COMPARATORS D 2 6 6 1 , J U N E 1 9 8 2 — R E V IS E D D E C E M B E R 1 9 8 3 S N 54A LS 677 . . . JT PACKAGE SN 74A LS 677 . . . .NT PACKAGE TOP VIEW • A L S 6 7 7 is a 16 -b it to 4-B it Comparator w ith Enable

Contextual Info: SN54AC74, SN74AC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET _SCASS21C- AUGUST 199S - REVISED SEPTEMBER 1996 EPIC Enhanced-Performance Implanted CMOS 1-|im Process SN54AC74 . . . J OR W PACKAGE SN74AC74 . . . D, DB, N, OR PW PACKAGE

75113

Contextual Info: • T -7S-4S-07 SN55113, SN75113 DUAL DIFFERENTIAL LINE DRIVERS 6=^1724 □0A223ci 7 « T i m TEXAS INSTR L IN /I N T F C * D 1 3 1 5 , SEPTEMBER 1 9 7 3 -R E V IS E O SEPTEM8ER 1 9 8 6 Choice of Open-Collector, Open-Emitter, or 3-State Outputs SN55113 . . . J PACKAGE

74179 register ic

Abstract: IC 74178 74179 4 bit shift register
Contextual Info: TYPES SN54178, SN54179, SN74178, SN74179 4-BIT PARALLEL-ACCESS SHIFT REGISTERS D E C E M B E R 1 9 7 2 -R E V IS E D D E C E M B E R 1983 Typical Maximum Clock Frequency . . . 39 MHz • Three Operating Modes: S N 7 4 1 7 8 . . . J OR N P A C K A G E TO P V IE W

Contextual Info: SN54AHCU04, SN74AHCU04 HEX INVERTERS SCLS234A - OCTOBER 1995 - REVISED MARCH 1996 SN54AHCU04 . . . J OR W PACKAGE SN74AHCU04. . . D, DB, N OR PW PACKAGE TOP VIEW Operating Range 2-V to 5.5-V V^c EPIC (Enhanced-Performance Implanted CMOS) Process Unbuffered Outputs

Contextual Info: T E X A S I N S T R -[ A S I C / N E M O R Y > 7 D D E | A T b l 7 2 S □ □ 3 S 7 E 0 T T -Hb-13-3-5 PRODUCT PREVIEW TBP38SA165, TBP38SA166, TBP38SA16X 16,384-BIT 2048 WORDS BY 8 BITS STANDARD PROGRAMMABLE READ-ONLY MEMORIES JAN UARY 1985 —REVISED APRIL 1985

SN 5477

Contextual Info: TYPES SN5475, SN5477, SN54L75, SN54L77, SN54LS75, SN54LS77, SN7475, SN74LS75 4-BIT BISTABLE LATCHES M A R C H 1 9 7 4 - R E V IS E D D E C E M B E R 1 9 8 3 S N 5475, SN 54LS75 . . J OR W PACKAGE S N 54L75 . . . J PACKAGE S N 7475 . . . J OR N PACKAGE SN74LS75 . , . D, J OR N PACKAGE

74LS636

Abstract: SN74LS636 SN54LS636 SN74LS637 74LS
Contextual Info: TYPES SN54LS636, SN54LS637, SN74LS636, SN74LS637 8-BIT PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS D 2 7 2 8 , A P R IL 1 9 8 3 , R E V IS E D D E C E M B E R 1983 SN 54LS' I PAC KA G E S N 7 4 L S ' . . . D W , J OR N P AC K A G E TO P V IE W Detects and Corrects Single-Bit Errors

Contextual Info: SN74LVCU04 HEX INVERTER SCAS282B - JANUARY 1993 - REVISED JULY 1995 D, DB, OR PW PACKAGE TOP VIEW • EP/C (Enhanced-Performance Implanted CMOS) Submicron Process I • ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model

Contextual Info: CDC2586 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS _SCAS337B- FEBRUARY 1 9 9 3 - REVISED NOVEMBER 1996 * f • • • • • • Low Output Skew for Clock-Dlstrlbutlon and Clock-Generation Applications Operates at 3.3-V Vqc Distributes One Clock Input to IWelve

TSL216

Contextual Info: TSL216 192 x 1 1NTEGRATED OPTO SENSOR SOESOO6-J U N E 1992 * Contains Three 64-Bit Static Shift Registers * Offers Extendable Data I/O for Expanding the Number of Sensors * * top v ie w Contains Analog Buffer With Sample-andHold for Analog Output Over Full Clock

ACT8841

Abstract: sn74act8841 SN74AS8840 S/ACT8841
Contextual Info: SN 74A C T8841 Digital Crossbar Switch The S N 7 4 A C T 8 8 4 1 is a single-chip digital crossbar sw itch that cost-effectively eliminates bottlenecks to speed data through com plex bus architectures. The 'A C T 8 8 4 1 has 16 four-bit bidirectional ports w hich can be connected in

pal16r

Contextual Info: TIBPAL16L8-5C, TIBPAL16R4-5C, TIBPAL16R6-5C, TIBPAL16R8-5C TIBPAL16L8-7M, TIBPAL16R4-7M, TIBPAL16R6-7M, TIBPAL16R8-7M HIGH-PERFORMANCE IM PACT-X PAL CIRCUITS S R P S 0 1 1D - D 3 3 5 9 O C T O B E R 1989 - R E V IS E D S E P T E M B E R 1992 • TIB P A L16L8