SN74AC74 Search Results

Contextual Info: SN54AC74, SN74AC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET _SCASS21C- AUGUST 199S - REVISED SEPTEMBER 1996 EPIC Enhanced-Performance Implanted CMOS 1-|im Process SN54AC74 . . . J OR W PACKAGE SN74AC74 . . . D, DB, N, OR PW PACKAGE

SN74AC74-EP

Contextual Info: SN54AC74, SN74AC74 DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOPS WITH CLEAR AND PRESET SCAS521F − AUGUST 1995 − REVISED OCTOBER 2003 D 2-V to 6-V VCC Operation D Inputs Accept Voltages to 6 V D Max tpd of 10 ns at 5 V SN54AC74 . . . J OR W PACKAGE

SN74AC74-EP

Contextual Info: SN54AC74, SN74AC74 DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOPS WITH CLEAR AND PRESET SCAS521F − AUGUST 1995 − REVISED OCTOBER 2003 SN54AC74 . . . J OR W PACKAGE SN74AC74 . . . D, DB, N, NS, OR PW PACKAGE TOP VIEW D 2-V to 6-V VCC Operation D Inputs Accept Voltages to 6 V

SN74AC74-EP

Contextual Info: SN74AC74ĆEP DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOP WITH CLEAR AND PRESET SCAS721 − OCTOBER 2003 D Controlled Baseline D D D D − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of −55°C to 125°C Enhanced Diminishing Manufacturing

SN74AC74-EP

Contextual Info: SN54AC74, SN74AC74 DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOPS WITH CLEAR AND PRESET SCAS521F − AUGUST 1995 − REVISED OCTOBER 2003 D 2-V to 6-V VCC Operation D Inputs Accept Voltages to 6 V D Max tpd of 10 ns at 5 V SN54AC74 . . . J OR W PACKAGE

AC74

Abstract: SN54AC74 SN74AC74 SN74AC74D SN74AC74DBR SN74AC74DR SN74AC74N SN74AC74NSR SN74AC74PW
Contextual Info: SN54AC74, SN74AC74 DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOPS WITH CLEAR AND PRESET SCAS521F − AUGUST 1995 − REVISED OCTOBER 2003 D 2-V to 6-V VCC Operation D Inputs Accept Voltages to 6 V D Max tpd of 10 ns at 5 V SN54AC74 . . . J OR W PACKAGE

SN74AC74-EP

Contextual Info: SN54AC74, SN74AC74 DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOPS WITH CLEAR AND PRESET SCAS521F − AUGUST 1995 − REVISED OCTOBER 2003 D 2-V to 6-V VCC Operation D Inputs Accept Voltages to 6 V D Max tpd of 10 ns at 5 V SN54AC74 . . . J OR W PACKAGE

AC74

Abstract: SN54AC74 SN74AC74 SN74AC74D SN74AC74DBR SN74AC74DR SN74AC74N SN74AC74NSR SN74AC74PW
Contextual Info: SN54AC74, SN74AC74 DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOPS WITH CLEAR AND PRESET SCAS521F − AUGUST 1995 − REVISED OCTOBER 2003 D 2-V to 6-V VCC Operation D Inputs Accept Voltages to 6 V D Max tpd of 10 ns at 5 V SN54AC74 . . . J OR W PACKAGE

SN74AC74-EP

Abstract: SN74AC74MDREP SN54AC74 SN74AC74
Contextual Info: SN74AC74ĆEP DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOP WITH CLEAR AND PRESET SCAS721 − OCTOBER 2003 D Controlled Baseline D D D D − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of −55°C to 125°C Enhanced Diminishing Manufacturing

Contextual Info: SN74AC74ĆEP DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOP WITH CLEAR AND PRESET SCAS721 − OCTOBER 2003 D Controlled Baseline D D D D − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of −55°C to 125°C Enhanced Diminishing Manufacturing

SN74AC74-EP

Contextual Info: SN54AC74, SN74AC74 DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOPS WITH CLEAR AND PRESET SCAS521F − AUGUST 1995 − REVISED OCTOBER 2003 D 2-V to 6-V VCC Operation D Inputs Accept Voltages to 6 V D Max tpd of 10 ns at 5 V SN54AC74 . . . J OR W PACKAGE

Contextual Info: SN54AC74, SN74AC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCAS521E – AUGUST 1995 – REVISED NOVEMBER 2002 D D D SN54AC74 . . . J OR W PACKAGE SN74AC74 . . . D, DB, N, NS, OR PW PACKAGE TOP VIEW 2-V to 6-V VCC Operation Inputs Accept Voltages to 6 V

AC74

Contextual Info: SN54AC74, SN74AC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCAS521D – AUGUST 1995 – REVISED SEPTEMBER 2002 D D D SN54AC74 . . . J OR W PACKAGE SN74AC74 . . . D, DB, N, NS, OR PW PACKAGE TOP VIEW 2-V to 6-V VCC Operation Inputs Accept Voltages to 6 V

Contextual Info: SN54AC74, SN74AC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCAS521C – AUGUST 1995 – REVISED SEPTEMBER 1996 D D EPIC  Enhanced-Performance Implanted CMOS 1-µm Process Package Options Include Plastic Small-Outline (D), Shrink Small-Outline

SN74AC74-EP

Abstract: SN74AC74 SN74AC74MDREP clr 160
Contextual Info: SN74AC74ĆEP DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOP WITH CLEAR AND PRESET SCAS721 − OCTOBER 2003 D Controlled Baseline D D D D − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of −55°C to 125°C Enhanced Diminishing Manufacturing

SN74AC74-EP

Abstract: SN74AC74PWR AC74 SN54AC74 SN74AC74 SN74AC74D SN74AC74DBR SN74AC74DR SN74AC74N SN74AC74NSR
Contextual Info: SN54AC74, SN74AC74 DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOPS WITH CLEAR AND PRESET SCAS521F − AUGUST 1995 − REVISED OCTOBER 2003 D 2-V to 6-V VCC Operation D Inputs Accept Voltages to 6 V D Max tpd of 10 ns at 5 V SN54AC74 . . . J OR W PACKAGE

SN74AC74-EP

Contextual Info: SN74AC74ĆEP DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOP WITH CLEAR AND PRESET SCAS721 − OCTOBER 2003 D Controlled Baseline D D D D − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of −55°C to 125°C Enhanced Diminishing Manufacturing

Contextual Info: SN54AC74, SN74AC74 DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOPS WITH CLEAR AND PRESET SCAS521F − AUGUST 1995 − REVISED OCTOBER 2003 D 2-V to 6-V VCC Operation D Inputs Accept Voltages to 6 V D Max tpd of 10 ns at 5 V SN54AC74 . . . J OR W PACKAGE

Contextual Info: SN54AC74, SN74AC74 DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOPS WITH CLEAR AND PRESET SCAS521F − AUGUST 1995 − REVISED OCTOBER 2003 D 2-V to 6-V VCC Operation D Inputs Accept Voltages to 6 V D Max tpd of 10 ns at 5 V SN54AC74 . . . J OR W PACKAGE

Contextual Info: SN54AC74, SN74AC74 DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOPS WITH CLEAR AND PRESET SCAS521F − AUGUST 1995 − REVISED OCTOBER 2003 D 2-V to 6-V VCC Operation D Inputs Accept Voltages to 6 V D Max tpd of 10 ns at 5 V SN54AC74 . . . J OR W PACKAGE

Contextual Info: SN54AC74, SN74AC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCAS521C – AUGUST 1995 – REVISED SEPTEMBER 1996 D D EPIC  Enhanced-Performance Implanted CMOS 1-µm Process Package Options Include Plastic Small-Outline (D), Shrink Small-Outline

SN74AC74-EP

Contextual Info: SN74AC74ĆEP DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOP WITH CLEAR AND PRESET SCAS721 − OCTOBER 2003 D Controlled Baseline D D D D − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of −55°C to 125°C Enhanced Diminishing Manufacturing

AC74

Abstract: SN54AC74 SN74AC74 SN74AC74D SN74AC74DBR SN74AC74DR SN74AC74N SN74AC74NSR SN74AC74PWR
Contextual Info: SN54AC74, SN74AC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCAS521E – AUGUST 1995 – REVISED NOVEMBER 2002 D D D SN54AC74 . . . J OR W PACKAGE SN74AC74 . . . D, DB, N, NS, OR PW PACKAGE TOP VIEW 2-V to 6-V VCC Operation Inputs Accept Voltages to 6 V

SN74AC74-EP

Contextual Info: SN54AC74, SN74AC74 DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOPS WITH CLEAR AND PRESET SCAS521F − AUGUST 1995 − REVISED OCTOBER 2003 D 2-V to 6-V VCC Operation D Inputs Accept Voltages to 6 V D Max tpd of 10 ns at 5 V SN54AC74 . . . J OR W PACKAGE