SUPERSPARC Search Results

STP2012

Abstract: SuperSPARC STP2016QFP
Contextual Info: STP2016 S un M ic r o e l e c t r o n ic s J u ly 1997 Clock-2 Generator DATA SHEET System Clock Generator D e s c r ip t io n The STP2016 Clock-2 Chip generates clock signals for components on the SBus and MBus. The MBus and SBus are used by SPARC processors, such as SuperSPARC™. The MBus is designed for multiprocessing MP , operating at

SuperSPARC

Abstract: Mbus master 250 slave circuit tmx390 STP1091-60
Contextual Info: S un M icroelectronics July 1997 Multi-Cache Controller DATA SHEET Integrated Cache Controller for SuperSPARC D e s c r ip t io n The STP1091 is a high-performance external cache controller for the STP1020 SuperSPARC and STP1021 (SuperSPARC-II) microprocessors. It is used when a large secondary cache or an interface to a non-MBus sys­

supersparc

Contextual Info: Preliminary STP5010A SPARC Technology Business November 1994 5 0 MHz SuperSPARC MBus Module DATA SHEET SuperSPARC Only MBus Module D e s c r i p t io n The STP5010A is one of the members of the SuperSPARC based MBus module products. The STP5010A is designed with the latest high performance superscalar SuperSPARC STP1020A micro­

Supersparc

Abstract: IEEE754 STP1021A
Contextual Info: STP1021A July 1997 SuperSPARC -II DATA SHEET SPARC v8 32-Bit Superscalar Microprocessor DESCRIPTION The STP1021A is a new member of the SuperSPARC-II family of microprocessor products. Like its predecessors STP1020N, STP1020 and STP1021 this new part is fully SPARC Version 8 compliant and is completely upward compatible with the earlier SPARC Version 7 implementations running over 9,400 SPARC applications and development

free mbus master

Abstract: SuperSPARC VOLTAGE REGULATOR 78 IEEE754 SS20 STP1021A STP5011D STP5011DMBUS75 M-BUS mbus controllers
Contextual Info: STP5011D July 1997 SuperSPARC -II MBus Modules DATA SHEET 75/85 MHz SuperSPARC-II + 1 MB E-Cache DESCRIPTION The STP5011D is the MBus module incorporating the latest SuperSPARC-II microprocessor. This module provides a CPU sub-system with the high performance superscalar SuperSPARC-II microprocessor STP1021A

STP2016

Abstract: SuperSPARC mbus 10 application STP2011 STP2016QFP mbus MCLK11 MOSC STP2012
Contextual Info: STP2016 July 1997 Clock-2 Generator System Clock Generator DATA SHEET DESCRIPTION The STP2016 Clock-2 Chip generates clock signals for components on the SBus and MBus. The MBus and SBus are used by SPARC processors, such as SuperSPARC™. The MBus is designed for multiprocessing MP , operating at

Contextual Info: STP1091 S un M ic r o e l e c t r o n ic s J u ly 1997 Multi-Cache Controller DATA SHEET Integrated Cache Controller for SuperSPARC D e s c r ip t io n The STP1091 is a high-perform ance external cache controller for the STP1020 SuperSPARC and STP1021

SuperSPARC

Abstract: STP1020 mbus sparc IEEE754 STP1021A instruction set Sun SPARC T4 instruction set Sun SPARC T6
Contextual Info: ST P 1021A S un M icro electro nics J u ly 1997 SuperSPARC -ll DATA SHEET SPARC v8 32-Bit Superscalar Microprocessor D e s c r ip t io n T h e ST P 1021A is a n e w m em b er o f the SuperSP A R C -II fam ily o f m icro p ro cesso r prod u cts. L ik e its p red eces­

supersparc

Abstract: Sun STP1021
Contextual Info: S un M icro electro nics July 1997 SuperSPARCT“-ll DATA SHEET SPARC v8 32-Bit Superscalar Microprocessor D e s c r ip t io n The STP1021A is a new member of the SuperSPARC-II family of microprocessor products. Like its predeces­ sors STP1020N, STP1020 and STP1021 this new part is fully SPARC Version 8 compliant and is completely

Contextual Info: Prelimina: SIARCTechnology STP1090A Business January Multi-Cache Controller ,TM DATA. SE ET Integrated Cache Controller for SuperSPARC D e s c r ip t io n The STP1090A is a high-perform ance external cache controller for the STP1020A SuperSPARC and STP1021 (SuperSPARC-II) microprocessors. It is used w hen a large secondary cache or an interface

thermal specifications

Contextual Info: Modules S T P 5 0 1 1D: SuperSPARC -ll MBus Modules 75/85 MHz SuperSPARC-ll + 1 MB D

supersparc

Abstract: mbr d type 51 pins connector mbus controllers
Contextual Info: Preliminary ^ SPARC Technology Business STP5022B November 1994 Dual 50 MHz SuperSPARC MBus Module DATA SHEET Dual SuperSPARC + E-Cache Module D e s c r i p t io n The STP5022B is a dual SuperSPARC based MBus module. It is designed with the latest high perfor­

SuperSPARC

Abstract: M-BUS
Contextual Info: Preliminary STP5011B SPARC Technology Business November 1994 60, 50 MHz SuperSPARC MBus Module DATA SHEET SuperSPARC + E-Cache MBus Module D e s c r i p t io n The STP501 IB is one of the members of the SuperSPARC based MBus module products. It is designed

TMx390

Abstract: SuperSPARC STP1020 STP1021A MAD19 STP1091 ADDR02 Mbus master 250 slave circuit stp1090 imad-26
Contextual Info: STP1091.frm Page 97 Monday, August 25, 1997 3:08 PM STP1091 July 1997 Multi-Cache Controller DATA SHEET Integrated Cache Controller for SuperSPARC DESCRIPTION The STP1091 is a high-performance external cache controller for the STP1020 SuperSPARC and STP1021 (SuperSPARC-II) microprocessors. It is used when a large secondary cache or an interface to a non-MBus system is required.

Contextual Info: STP2016 S un M ic r o e l e c t r o n ic s J u ly 1 9 9 7 Clock-2 Generator System Clock Generator DATA SHEET D e s c r ip t io n The STP2016 Clock-2 Chip generates clock signals for com ponents on the SBus and MBus. The M Bus and SBus are used by SPARC processors, such as SuperSPARC™. The M Bus is designed for multiprocessing

tmx390

Abstract: supersparc PM 438 BL capacitor 471 aj7 tmx390x55 tpvc01
Contextual Info: STP1091.frm Page 97 Monday, August 25, 1997 3:08 PM S un M ic r o e l e c t r o n ic s July 1997 Multi-Cache Controller DATA SHEET Integrated Cache Controller for SuperSPARC D e s c r ip t io n The STP1091 is a high-performance external cache controller for the STP1020 SuperSPARC and STP1021 (Super­

STP1020

Abstract: DATA45 MAD42
Contextual Info: Prelimina Sun STP1020 May 19 94 SuperSPARC DÄIA SEET Highly Integrated 32-Bit RISC Microprocessor D e s c r ip t io n The STP1020 is one of the mem bers of the SuperSPARC fam ily of microprocessor products. Like the other members STP1020N and STP1020A , this part is fully SPARC version 8 com pliant and is com ­

Contextual Info: STP1021A S un M ic r o e l e c t r o n ic s J u ly 1997 SuperSPARC -ll DATA SHEET SPARC v8 32-Bit Superscalar Microprocessor D e s c r ip t io n The STP1021A is a new m em ber of the SuperSPARC-II fam ily of m icroprocessor products. Like its predeces­

Contextual Info: Preliminary w STP1020A SPARC Technology Business June 1995 SuperSPARC DATA SHEET Highly Integrated 32-Bit RISC Microprocessor D e s c r i p t io n The STP1020A is a new member of the SuperSPARC family of microprocessor products. Like its pre­ decessors STP1020N and STP1020 this new part is fully SPARC version 8 compliant and is completely

lcd cross reference

Abstract: SME2411BGA SuperSPARC 805-0086-02 PMC cross reference STP2003QFP ATM622-S STP3010 STP2014QFP STP2024QFP
Contextual Info: S un M icroelectronics July 1997 Data Sheets listed by Product Name Cross Reference List Advanced PCI Bridge SME2411BGA ATM622-S SAR SME4050BGA 802-7894-02 Color LCD Controller STP3031 STP3031 Crossbar Switch XB1 STP2230SOP 802-7955-02 Dual System Controller

SuperSPARC

Abstract: pnp Octal Darlington Transistor Arrays SN74FB2031 ABT16245 ABT245 scba001a signal path designer
Contextual Info: ABT Enables Optimal System Design SCBA001A March 1997 1 IMPORTANT NOTICE Texas Instruments TI reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest

SuperSPARC

Abstract: CY7C37256 CY7B923 CY7B933 CY7C4285 CY7C43644V CY7C43664V CY7C43682AV CY7C43684V CY7C436X6
Contextual Info: Designing with CY7C436xx Synchronous FIFOs Cypress Semiconductor offers four families of x36 FIFOs in 3.3V and 5V versions: The unidirectional with Bus Matching CY7C436x3AV/CY7C436x3, the bidirectional CY7C436x2AV /CY7C436x2, the bidirectional with Bus Matching

AXP 209 IC

Abstract: AXP 193 AXP 188 AXP 188 IC AXP 199 AXP 209 Datasheet AXP 209 80486DX architecture mb86900 486DX2
Contextual Info: Benchmarking the Am186EM Using the Dhrystone V2.1 as an example Don Gille Sr. Field Application Engineer Advanced Micro Devices Inc. Table of Contents

ic master 1997

Contextual Info: ÜG July 1997 Master I/O 32-bit SBus Master I/O Controller DATA SHEET D e s c r ip t io n The STP2000 Master I/O Controller is an integrated SBus master device with built-in standard I/O capabili­ ties for general purpose computing or embedded applications. The STP2000 directly interfaces the CPU