DATA49 Search Results

SuperSPARC

Abstract: Mbus master 250 slave circuit tmx390 STP1091-60
Contextual Info: S un M icroelectronics July 1997 Multi-Cache Controller DATA SHEET Integrated Cache Controller for SuperSPARC D e s c r ip t io n The STP1091 is a high-performance external cache controller for the STP1020 SuperSPARC and STP1021 (SuperSPARC-II) microprocessors. It is used when a large secondary cache or an interface to a non-MBus sys­

Contextual Info: Advance Data Sheet August 1998 LU5M31 Gigabit Ethernet Media Access Controller MAC Overview The LU5M31 is a single-port 1 Gbit/s MAC that incorporates physical coding sublayer (PCS) functionality. The LU5M31 is intended to enhance 10/ 100 Mbits/s Ethernet frame switching, multiple port

clause 22 phy registers

Abstract: 13007 h3 ali 3602 detail of D 13007 K mca exam date sheet 1000BASE-X DS1005 STS-48
Contextual Info: LatticeSC/M Family flexiPCS Data Sheet DS1005 Version 01.9, December 2008 LatticeSC/M Family flexiPCS Data Sheet Table of Contents December 2008 Introduction to flexiPCS .1-1

SMD45

Abstract: SMD34 224 d5 smd zd 15 p240f1 SMD52 SMD46 SMD-42 smd M16 SMD23
Contextual Info: お客様各位 カタログ等資料中の旧社名の扱いについて 2010 年 4 月 1 日を以って NEC エレクトロニクス株式会社及び株式会社ルネサステクノロジ が合併し両社の全ての事業が当社に承継されております。従いまして、本資料中には旧社

AT17256

Abstract: 7Pin din Connector AN076 qfp 32 k2511 phillips handbook XPLA1 UNSIGNED SERIAL DIVIDER using vhdl
Contextual Info: APPLICATION NOTE AN076 Using the Philips PZ3960 Evaluation Board 1998 Jul 21 Philips Semiconductors Application note Using the Philips PZ3960 Evaluation Board AN076 INTRODUCTION This note discusses the use of the Philips PZ3960 evaluation board. The main functions of the evauation board are the

Contextual Info: To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid

SMD phase shifter 0201

Abstract: ts201S ADSP-TS201SABP-050 ADSP-TS201SABP-060 l3bc
Contextual Info: TigerSHARC Embedded Processor ADSP-TS201S • a KEY FEATURES KEY BENEFITS Up to 600 MHz, 1.67 ns instruction cycle rate 24M bits of internal—on-chip—DRAM memory 25 mm x 25 mm 576-ball thermally enhanced ball grid array package Dual-computation blocks—each containing an ALU, a

led dot matrix drive schematics

Abstract: P-SSOP30-300-0 TB62727 TB62727FN 1S1830
Contextual Info: TOSHIBA TB62727FN TOSHIBA Bi-CMOS INTEGRATED CIRCUIT SILICON MONOLITHIC TB62727FN 16-bit constant current LED module with built-in dot-current correction for each output The TB62727FN is an LED-driver suitable for lighting single-color and full-color LED modules and panels.

Supersparc

Abstract: IEEE754 STP1021A
Contextual Info: STP1021A July 1997 SuperSPARC -II DATA SHEET SPARC v8 32-Bit Superscalar Microprocessor DESCRIPTION The STP1021A is a new member of the SuperSPARC-II family of microprocessor products. Like its predecessors STP1020N, STP1020 and STP1021 this new part is fully SPARC Version 8 compliant and is completely upward compatible with the earlier SPARC Version 7 implementations running over 9,400 SPARC applications and development

TDSR 5130

Abstract: TDSR 5130 H TDSR 5130 g TDSR SQFP208 SAA6750H SAA7111 SAA7146 iso 13818-2 SAA711x
Contextual Info: INTEGRATED CIRCUITS DATA SHEET SAA6750H Encoder for MPEG2 image recording EMPIRE Preliminary specification File under Integrated Circuits, IC02 1998 Sep 07 Philips Semiconductors Preliminary specification Encoder for MPEG2 image recording (EMPIRE) SAA6750H

clause 22 phy registers

Contextual Info: LatticeSC Family flexiPCS Data Sheet DS1005 Version 01.2, June 2006 LatticeSC flexiPCS Data Sheet Table of Contents June 2006 Introduction to flexiPCS .1-1

EE-68

Abstract: ts201 Embedded Processor Preliminary Data Sheet link port ts201 32X32 ADSP-TS201S l3bc ADSP-TS201SABP-6X ADSP-TS201SABP-X
Contextual Info: TigerSHARC Embedded Processor ADSP-TS201S Preliminary Technical Data KEY FEATURES KEY BENEFITS Up to 600 MHz, 1.67 ns Instruction Cycle Rate 24M Bits of Internal—On-Chip—DRAM Memory 25x25 mm 576-Ball Thermally Enhanced Ball Grid Array Package Dual Computation Blocks—Each Containing an ALU, a Multiplier, a Shifter, a Register File, and a Communications Logic

Contextual Info: SONY PRELIMINARY SCM603256A5 Cache Module for PowerPC 603e CPU PowerPC 603e 256KB Secondary Cache Description The SCM603256A5 module belongs to a set of sec­ ondary caches intended for use with PowerPC 603e based systems. The SCM603256A5 uses two of Sony’s 1M 32Kx32

supersparc

Abstract: HY 1021A Sun STP1021 3AR3 cap 220 htz ADA33
Contextual Info: [ f ^ T l r í A C K j S un M i c r o e l e c t r o n i c s July 1997 SuperSPARC“-ll DATA SHEET SPARC v8 32-Bit Superscalar Microprocessor D e s c r ip t io n The STP1021A is a new m em ber of the Su p erSPA R C T I fam ily o f m icroprocessor products. L ik e its predeces­

PB-MV40

Abstract: Photobit MV40 D100 D109 D110 D119 D120 D129 D130
Contextual Info: PB-MV40 4 Megapixel CMOS Active-Pixel Digital Image Sensor 2001 Photobit Technology Corporation. All rights reserved. Photobit Technology Corporation is a wholly owned subsidiary of Photobit Corporation. Photobit, the wave and binary symbol, Behind Every Great Digital Image, and TrueBit are registered trademarks-and TrueColor, TrueSNAP Shuttered-Node

GHW Connectors

Abstract: TDQ38 BTA60 bta61 bta80 bta11 BTA100 BTA32 bta50 bta81
Contextual Info: Version 1.2 December 1999 2975 Stender Way, Santa Clara, California 95054 Telephone: 800 345-7015 • TWX: 910-338-2070 • FAX: (408) 492-8674 Printed in U.S.A. 1999 Integrated Device Technology, Inc. Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance

Contextual Info: STP1091 S un M ic r o e l e c t r o n ic s J u ly 1997 Multi-Cache Controller DATA SHEET Integrated Cache Controller for SuperSPARC D e s c r ip t io n The STP1091 is a high-perform ance external cache controller for the STP1020 SuperSPARC and STP1021

sot23-6 aa3

Abstract: l3bc ST-323-5 ADSP-TS201 SDRAM W17 sot23 micro usb 8pin schematic AE1233-ND p-channel mosfet m21 D44 SOT23-6 B20 SOT23-6
Contextual Info: ADSP-TS201S EZ-KIT Lite Evaluation System Manual Revision 1.0, March 2004 Part Number 82-000770-01 Analog Devices, Inc. One Technology Way Norwood, Mass. 02062-9106 a Copyright Information 2004 Analog Devices, Inc., ALL RIGHTS RESERVED. This document may not be reproduced in any form without prior, express written

32x32 Multiplier

Abstract: EE-174 32X32 ADSP-TS201S processor cross reference avr ms1 diagram ADSP-TS201SABP-ENG
Contextual Info: PRELIMINARY TECHNICAL DATA TigerSHARC Embedded Processor ADSP-TS201S a Preliminary Technical Data KEY FEATURES 500 MHz, 2.0 ns Instruction Cycle Rate 24M Bits of Internal—On-Chip—DRAM Memory 25؋25 mm 576-Ball Thermally Enhanced Ball Grid Array Package

RFID tag

Abstract: ISO 14443-4 14443-4 command TAG 106 D A9211-B A9211B 14443-4 rfid circuit diagram rfid RFID protocol communication
Contextual Info: A9211B ISO/IEC 14443A RFID TAG IC FEATURE OTP Memory – – Compatible with ISO/IEC 14443A Standard 224 x 8 bits of data memory organized in 56 pages – No external power supply required – – 13.56MHz operating frequency – Total embedded 2048 bit OTP memory

ADSP-TS201 SDRAM

Abstract: TigerSHARC DSP Instruction set specification ADSP-TS201
Contextual Info: TigerSHARC Embedded Processor ADSP-TS202S a KEY FEATURES 1149.1 IEEE-compliant JTAG test access port for on-chip emulation On-chip arbitration for glueless multiprocessing 500 MHz, 2.0 ns instruction cycle rate 12M bits of internal—on-chip—DRAM memory

PB-MV13

Abstract: Photobit PB-1024 PHILIPS mpr24 8097 architecture MV13 DATA-71 data61 Data72 Photobit 720
Contextual Info: PB-MV13 20mm CMOS Active-Pixel Digital Image Sensor 2000 Photobit Corporation. All rights reserved. Photobit, the wave and binary symbol, and Behind Every Great Digital Image are registered trademarks, and TrueBit, TrueColor, TrueSNAP Shuttered-Node Active Pixel , Fully Flexible Open Architecture, Serial Host Interface Port, and Leading the Active Pixel Revolution are trademarks, of Photobit Corporation in

clause 22 phy registers

Contextual Info: LatticeSC Family flexiPCS Data Sheet DS1005 Version 01.5, March 2007 LatticeSC flexiPCS Data Sheet Table of Contents March 2007 Introduction to flexiPCS .1-1

74ALVT16652

Abstract: CYNCP80192 CYNSE70032 CYNSE70128
Contextual Info: CYNCP80192 CYNCP80192 Network Database Coprocessor Cypress Semiconductor Corporation Rev. * • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 April 20, 2001 CYNCP80192 CONTENTS 1.0 OVERVIEW . 1