DS1005 Search Results

clause 22 phy registers

Abstract: 13007 h3 ali 3602 detail of D 13007 K mca exam date sheet 1000BASE-X DS1005 STS-48
Contextual Info: LatticeSC/M Family flexiPCS Data Sheet DS1005 Version 01.9, December 2008 LatticeSC/M Family flexiPCS Data Sheet Table of Contents December 2008 Introduction to flexiPCS .1-1

DS1425L-F5

Abstract: rtc ds1307 dallas ds2501 dallas ds2501 Datasheet dallas ds1280 DS2501 ds1642-150 DS1669 replacement ds2501 Datasheet DS1608S
Contextual Info: ORDERING INFORMATION DEVICE DS0621–SDK DS0630 DS1000 DS1000–IND DS1003 DS1004 DS1005 DS1007 DS1010 DS1012 DS1013 DS1020 DS1021 DS1033 DS1035 DS1040 PACKAGE TYPE Software Software 14–Pin DIP 8–Pin DIP 16–Pin SOIC 8–Pin SOIC 8–Pin DIP 8–Pin SOIC

clause 22 phy registers

Contextual Info: LatticeSC Family flexiPCS Data Sheet DS1005 Version 01.2, June 2006 LatticeSC flexiPCS Data Sheet Table of Contents June 2006 Introduction to flexiPCS .1-1

9721

Abstract: ABLEBONd 84-1 JEDEC hast
Contextual Info: 03/24/2003 RELIABILITY REPORT FOR DS1005, Rev A2 Dallas Semiconductor 4401 South Beltwood Parkway Dallas, TX 75244-3292 Prepared by: Ken Wendel Reliability Engineering Manager Dallas Semiconductor 4401 South Beltwood Pkwy. Dallas, TX 75244-3292 Email : ken.wendel@dalsemi.com

74LS

Abstract: DS1005 DS1005-100 DS1005-125 DS1005-60 DS1005-75 DS1005M DS1005S
Contextual Info: DS 1005 DALLAS r DS1005 5-Tap Silicon Delay Line s e m ic o n d u c to r FEATURES PIN ASSIGNMENT • All-silicon time delay IN 1 14 ] Vcc IN £ 1 16 H VCC NC 2 13 ] NC NC C 2 15 n NC C 3 14 H NC NC 3 12 TAP 2 C 4 13 H TAP 1 • Stable and precise over temperature and voltage

Contextual Info: DALLAS SEMICONDUCTOR DS1005 5-Tap Silicon Delay Line PIN ASSIGNMENT FEATURES • All-silicon time delay IN • 5 taps equally spaced NC • Delay tolerance ±2 ns or ±3%, whichever is greater NC • Stable and precise over temperature and voltage range TAP 2

clause 22 phy registers

Contextual Info: LatticeSC Family flexiPCS Data Sheet DS1005 Version 01.5, March 2007 LatticeSC flexiPCS Data Sheet Table of Contents March 2007 Introduction to flexiPCS .1-1

74F04

Abstract: 74LS DS1005 DS1005-150 DS1005-60 DS1005-75 DS1005M DS1005S
Contextual Info: DS1005 5-Tap Silicon Delay Line www.dalsemi.com PIN ASSIGNMENT FEATURES • All-silicon time delay IN Q 1 W 14 IN Q 1 W 16 VCc Vcc ■ 5 taps equally spaced NC Q 2 13 NC NC Q 2 15 ] NC ■ Delay tolerance ±2 ns or ±3%, whichever is greater NC Q 3 12 TAP 1

Contextual Info: DS1005 DALLAS DS1005 5-Tap Silicon Delay Line s e m ic o n d u c t o r FEATURES PIN DESCRIPTION • All-silicon time delay • 5 taps equally spaced itC 1 14 ] V c c nc£ 2 13 3 12 ]]TAP 1 TAP 4 Ü Delay tolerance +/- 2 ns or +/- 2%, whichever ncQ is greater

74LS

Abstract: DS1005 DS1005-100 DS1005-125 DS1005-150 DS1005-75 DS1005M DS1005S delay line 400ns
Contextual Info: DALLAS SEMICO ND UCTOR CORP OTE D | 2bl4130 □□□2074 b | T-47-13 ^ Dallas Semiconductor 5 TAP SILICON DELAY LINE 31 FEATURES DS1005 14-Pin DIP DS1005M 8-Pin DIP DS1005S 16-Pin SOIC PIN CONNECTIONS • All silicon time delay . • 5 TAPS equally spaced. Delay

74LS

Abstract: DS1005 DS1005-60 DS1005G DS1005H DS1005K DS1005M DS1005S
Contextual Info: DS1005 DALLAS SEMICONDUCTOR DS1005 5-Tap Silicon Delay Line PIN ASSIGNMENT FEATURES • All-silicon time delay IN • 5 taps equally spaced • Delay tolerance ±2 ns or ±3%, whichever is greater • Stable and precise over temperature and voltage range • Leading and trailing edge accuracy

DS1005-60

Abstract: 74LS DS1005 DS1005-100 DS1005-125 DS1005-150 DS1005-175 DS1005-75 DS1005M DS1005S
Contextual Info: DS1005 5-Tap Silicon Delay Line www.dalsemi.com FEATURES All-silicon time delay 5 taps equally spaced Delay tolerance ±2 ns or ±3%, whichever is greater Stable and precise over temperature and voltage range Leading and trailing edge accuracy Economical Auto-insertable, low profile

Contextual Info: DS1005 PALLAS DS1005 SEMICONDUCTOR 5-Tap Silicon Delay Line FEATURES PIN ASSIGNMENT • All-silicon time delay IN • 5 taps equally spaced NC r L NC r L • Delay tolerance ±2 ns or ±3%, whichever is greater • Stable and precise over temperature and voltage

74FO4

Contextual Info: 19-1309; Rev 0; 10/97 5-Tap Silicon Delay Line _Features ♦ Improved Second Source to DS1005 ♦ Available in Space-Saving 8-Pin µMAX Package ♦ 17mA Supply Current vs. Dallas’ 40mA ♦ Low Cost ♦ Delay Tolerance of ±2ns or ±3%, whichever is

clause 22 phy registers

Contextual Info: LatticeSC/M Family flexiPCS Data Sheet DS1005 Version 01.6, August 2007 LatticeSC/M flexiPCS Data Sheet Table of Contents August 2007 Introduction to flexiPCS .1-1

DS1669-100

Abstract: TQFP 100 pin Socket 4 pin dip switch DS2401 PACKAGE 16 pin DIP socket DS1804 NV 2 pin dip switch ds1232(ind) data sheet ds1642-150 DS1620S
Contextual Info: ORDERING INFORMATION DEVICE DS0621–SDK DS1000 DS1000–IND DS1003 DS1004 DS1005 DS1007 DS1010 DS1012 DS1013 DS1020 DS1021 DS1033 DS1035 DS1040 PACKAGE TYPE Software 14–Pin DIP 8–Pin DIP 16–Pin SOIC 8–Pin SOIC 8–Pin DIP 8–Pin SOIC 14–Pin DIP

marking code 214

Abstract: "Dallas Semiconductor" TOP MARKING 6K MARKING CODE dALLAS MARKING CODE K428 DS1000M-500 PECVD DS1000 DS1000M DS1000S
Contextual Info: DALLAS SEMICONDUCTOR 4401 South Beltwood Parkway Dallas, Texas 75244–3292 214 450–0400 Date: January 12, 1994 To: Subject: PRODUCT CHANGE NOTICE – K42801 Description: Alternate Passivation Scheme for DS1000–500 and DS1005 Description of Change The products listed below currently are being converted from a passivation scheme consisting of 4KÅ

6V-0-6V

Abstract: precision waveform generator hy 214 74LS DS1005 DS1005-100 DS1005-125 DS1005-60 DS1005-75 DS1005M
Contextual Info: DS1005 DS1005 5-Tap Silicon Delay Line FEATURES PIN ASSIGNMENT • All-silicon time delay • 5 taps equally spaced IN 1 14 Vcc IN 1 16 VCC NC 2 13 NC NC 2 15 NC • Delay tolerance ±2 ns or ±3%, whichever is greater NC 3 12 TAP 1 TAP 2 4 11 NC NC 5 10 TAP 3

Contextual Info: DS1005 DALLAS SEMICONDUCTOR DS1005 5-Tap Silicon Delay Line FEATURES PIN ASSIGNMENT • All-silicon time delay C1 c2 NC [ 3 TAP 2 c4 NC [ 5 TAP 4 [ 6 GND [ 7 IN • 5 taps equally spaced NC • Delay tolerance ±2 ns or ±3%, whichever is greater • Stable and precise over temperature and voltage

Contextual Info: DS1005 DALLAS SEMICONDUCTOR DS1005 5-Tap Silicon Delay Line FEATURES PIN ASSIGNMENT • All-silicon time delay IN [ • 5 taps equally spaced NC [ C 1 14 3 Vcc IN C 1 2 13 ] NC NC £ 2 3 12 ] TAP1 4 11 10 ] TAPS NC C 3 • Delay tolerance ± 2 ns or ±3%, whichever is greater

ic DS2430

Abstract: ds1205v DS1640
Contextual Info: M E C H A N IC A L D R A W IN G S 8 - TO 28-PIN DIP 300 MIL Includes: DS1000 DS1000M DS1003 DS1003M DS1004M DS1005 DS1005M DS1007 DS1010 DS1012M DS1013 DS1013M DS1020 DS1033M DS1035M DS1040M DS1044 DS1045 DS1200 DS1206 DS1210 8-PIN PKG 10-PIN 14-PIN 16-PIN

DS1425L-F5

Abstract: ds1480s F5 sot223 DS1868 DS75U ds1642-150 DS1669SN-10 DS1220Y-200IND ds1386-8-150 DS1251W-120
Contextual Info: DEVICE DS0621 DS1000 DS1000-IND DS1004 DS1005 DS1007 DS1010 DS1013 DS1020 PACKAGE TYPE OPERATING TEMPERATURORDERING RANGE CELSIUS NUMBER Software 8-Pin DIP 8-Pin SOIC 8-Pin SOIC T&R 8-Pin DIP 8-Pin SOIC 8-Pin SOIC T&R 8-Pin DIP 8-Pin DIP 8-Pin DIP 8-Pin DIP

clause 22 phy registers

Contextual Info: LatticeSC/M Family flexiPCS Data Sheet DS1005 Version 01.8, June 2008 LatticeSC/M flexiPCS Data Sheet Table of Contents June 2008 Introduction to flexiPCS .1-1

clause 22 phy registers

Contextual Info: LatticeSC/M Family flexiPCS Data Sheet DS1005 Version 01.9, December 2008 LatticeSC/M Family flexiPCS Data Sheet Table of Contents December 2008 Introduction to flexiPCS .1-1