DS1044 Search Results

"Delay Lines"

Abstract: 74F04 DS1035 DS1044 DS1044R
Contextual Info: DS1044 DS1044 4–in–1 High–Speed Silicon Delay Line FEATURES PIN ASSIGNMENT • All–silicon timing circuit IN1 1 14 VCC NC 2 13 NC IN2 3 12 OUT1 IN3 4 11 NC IN4 5 10 OUT2 NC 6 9 OUT3 GND 7 8 OUT4 • Four independent buffered delays • Initial delay tolerance ±1.5 ns

14-PIN

Contextual Info: DS1044 DS1044 4 —¡n—1H igh-Speed Silicon Delay Line PIN ASSIGNMENT NC • Initial delay tolerance ±1.5 ns IN2 IN3 • Stable and precise over temperature and voltage IN4 • Leading and trailing edge precision preserves the input symmetry NC GND • Standard 14-pin DIP, 14-pin SOIC 150 mil

74F04

Abstract: DS1035 DS1044 DS1044R DIP SWITCH EDGE
Contextual Info: DS1044 DS1044 4–in–1 High–Speed Silicon Delay Line FEATURES PIN ASSIGNMENT • All–silicon timing circuit IN1 1 14 VCC NC 2 13 NC IN2 3 12 OUT1 IN3 4 11 NC IN4 5 10 OUT2 NC 6 9 OUT3 GND 7 8 OUT4 • Four independent buffered delays • Initial delay tolerance ±1.5 ns

37143

Contextual Info: DS1044 DALLAS SEMICONDUCTOR DS1044 4—in— 1 High-Speed Silicon Delay Line FEATURES PIN ASSIGNMENT • All-silicon timing circuit NC • Initial delay tolerance ±1.5 ns IN2 IN3 • Stable and precise over temperature and voltage IN4 • Leading and trailing edge precision preserves the

56-G2008-001C

Contextual Info: DS1044 DS1044 4–in–1 High–Speed Silicon Delay Line FEATURES PIN ASSIGNMENT • All–silicon timing circuit IN1 1 14 VCC NC 2 13 NC IN2 3 12 OUT1 IN3 4 11 NC IN4 5 10 OUT2 NC 6 9 OUT3 GND 7 8 OUT4 • Four independent buffered delays • Initial delay tolerance ±1.5 ns

Contextual Info: DS1044 PRELIMINARY D ALLAS SEMICONDUCTOR DS1044 4 — in— 1 H i g h - S p e e d Silicon Delay Line FEA TU R E S PIN A S S IG N M E N T • A ll-s ilic o n timing circuit IN 1 * Fo ur in d e p e n d e n t buffered de lays NC • Initial de lay toler an ce ±1.5 ns

DS1044G

Contextual Info: DS1044 PRELIMINARY DS1944 4—in—1 High-Speed Silicon Delay Line FEATURES PIN ASSIGNMENT • All-silicon timing circuit IN1 C1 14 • Four independent buffered delays NC 2 13 • Initial delay tolerance ±1.5 ns IN2 3 12 4 11 IN3 • Stable and precise over temperature and voltage

Contextual Info: ECP5 Family Data Sheet Preliminary DS1044 Version 1.2, August 2014 ECP5 Family Data Sheet Introduction August 2014 Preliminary Data Sheet DS1044 Features  Higher Logic Density for Increased System Integration  Pre-Engineered Source Synchronous I/O

0223

Abstract: DS1035 DS1044 DS1044-10 DS1044G DS1044R
Contextual Info: DS1044 PRELIMINARY DALLAS s e m ic o n d u c to r DS1044 4—in—1 High-Speed Silicon Delay Line FEATURES PIN ASSIGNMENT • All-silicon timing circuit IN1 • Four independent buffered delays NC • Initial delay tolerance ±1.5 ns IN2 IN3 • Stable and precise over temperature and voltage

DALLAS DS

Contextual Info: DS 1044 DALLAS SEMICONDUCTOR DS1044 4—in—1 H igh -S pe ed Silicon Delay Line FEATURES PIN ASSIGNMENT • A ll-silico n timing circuit NC • Initial delay tolerance ±1.5 ns IN2 IN3 • Stable and precise over tem perature and voltage IN4 • Leading and trailing edge precision preserves the

Contextual Info: DS1044 4-in-1 High-Speed Silicon Delay Line www.dalsemi.com FEATURES PIN ASSIGNMENT All-silicon timing circuit Four independent buffered delays Initial delay tolerance ±1.5 ns Stable and precise over temperature and voltage Leading and trailing edge precision preserves

Contextual Info: ECP5 Family Data Sheet Advance DS1044 Version 1.1, June 2014 ECP5 Family Data Sheet Introduction March 2014 Advance Data Sheet DS1044 Features  Higher Logic Density for Increased System Integration  Pre-Engineered Source Synchronous I/O • • •

Contextual Info: DS1044 DALLAS SEMICONDUCTOR D S1044 4 -in -1 H igh-Speed Silicon Delay Line FEATURES PIN ASSIGNMENT C 1 14 1 2 13 : NC 3 12 : OUT1 c 4 11 : NC : 5 10 : OUT2 : 6 9 : OUT3 : 7 8 : OUT4 • Four independent buffered delays z o 1N1 < o o • All-silicon timing circuit

DS1035

Abstract: DS1044 DS1044-10 DS1044-12 DS1044-5 DS1044-6 DS1044-7 DS1044-8 DS1044R
Contextual Info: DS1044 DALLAS SEMICONDUCTOR D S1044 4 -in -1 H igh-Speed Silicon Delay Line FEATURES PIN ASSIGNMENT C 1 14 1 2 13 : NC 3 12 : OUT1 c 4 11 : NC : 5 10 : OUT2 : 6 9 : OUT3 : 7 8 : OUT4 • Four independent buffered delays z o 1N1 < o o • All-silicon timing circuit

Contextual Info: D S 1044 DALLAS DS1044 4—in—1 High-Speed Silicon Delay Line s e m ic o n d u c t o r PIN ASSIGNMENT FEATURES • A ll-silicon timing circuit IN1 c 1 14 H Vcc • Four independent buffered delays NC [ [ 2 13 H NC • Initial delay tolerance ±1.5 ns IN2 Q

Contextual Info: ECP5 Family Data Sheet Advance DS1044 Version 01.0, March 2014 ECP5 Family Data Sheet Introduction March 2014 Advance Data Sheet DS1044 Features  Higher Logic Density for Increased System Integration  Pre-Engineered Source Synchronous I/O • •

ic DS2430

Abstract: ds1205v DS1640
Contextual Info: M E C H A N IC A L D R A W IN G S 8 - TO 28-PIN DIP 300 MIL Includes: DS1000 DS1000M DS1003 DS1003M DS1004M DS1005 DS1005M DS1007 DS1010 DS1012M DS1013 DS1013M DS1020 DS1033M DS1035M DS1040M DS1044 DS1045 DS1200 DS1206 DS1210 8-PIN PKG 10-PIN 14-PIN 16-PIN

DS-1135

Abstract: DS1100 programmable delay DS1000 DS1004 DS1005 DS1007 DS1020 DS1033 DS1040
Contextual Info: Maxim > App Notes > COMMUNICATIONS CIRCUITS OSCILLATORS/DELAY LINES/TIMERS/COUNTERS Keywords: delay lines, silicon timed circuits, dealy lines, STCs, DS1040, DS1135L, DS1020, DS1045, DS1033, DS1044, DS1007, DS1000, DS1004, DS1005, DS1100, DS1100L, DS1010, DS1021, DS1013, DS1035,

74F04

Abstract: DS1035 DS1044 DS1044R
Contextual Info: DS1044 DS1044 4–in–1 High–Speed Silicon Delay Line FEATURES PIN ASSIGNMENT • All–silicon timing circuit IN1 1 14 VCC NC 2 13 NC IN2 3 12 OUT1 IN3 4 11 NC IN4 5 10 OUT2 NC 6 9 OUT3 GND 7 8 OUT4 • Four independent buffered delays • Initial delay tolerance ±1.5 ns

cen 496

Abstract: DS1868 DS1000H DS1205V DS1640
Contextual Info: M E C H A N IC A L D R A W IN G S 8 - TO 28-PIN DIP 300 MIL mr~ i r~ i i— i nn n n Includes: DS1000 DS1000M DS1003 DS1003M DS1004M DS1005 DS1005M DS1007 DS1010 DS1012M DS1013 DS1013M DS1020 DS1033M DS1035M DS1040M DS1044 DS1045 DS1200 DS1206 DS1210 PKG

DS1666

Abstract: DS2011D 74F04 DS1003 DS1003-16 DS1003-20 DS1003-25 DS1003-33 DS1003-40 DS1003M
Contextual Info: DS1003 DS1003 DALLAS SEMICONDUCTOR FEATURES 4-Tap Silicon Delay Line for RISC A pplications PIN ASSIGNMENT • All-silicon tim e delay IN • Four delayed clock phases from input NC • Input frequency independent NC NC • Precise tap-to-tap delays • Leading and trailing edge precision

ds1285q

Abstract: DS1640
Contextual Info: D S 12 8 5 /D S 1285Q DALLAS SEMICONDUCTOR FEATURES D S 1285/D S 1285Q Real Tim e C lock PIN ASSIGNMENT • Drop-in replacem ent for IBM AT com puter clock/ca­ lendar • Pin configuration closely m atches M C146818A • Counts seconds, minutes, hours, day of the week,

DS1640

Contextual Info: DS1668, DS1669, DS1669S DALLAS SEMICONDUCTOR DS1668, DS1669, DS1669S D allastat Electronic Digital Rheostat FEATURES PIN ASSIGNMENT DS1669 • Replaces mechanical variable resistors • Available as the DS1668 with manual interface or the DS1669 integrated circuit

DS1640

Contextual Info: DS129X DALLAS SEMICONDUCTOR FEATURES • Replaces 8 or 16 h a rd -to -g e t-a t m anual switches DS129x Elim inator PIN ASSIGNMENT GND2 [ 24 ] GND3 2 23 ] VCC T 23Ì VCC Dl [ 3 22 ] OA Dl 22Ì OA OQ [ 4 21 ] OB OQ 211 OB 00 5 20 ] OC 00 oe ON [ 6 19 ] OD om