MCLK10 Search Results

bms 16s

Abstract: SWBT13 UT1553BCRTM ta306
Contextual Info: UT1553 BCRTM p Register-oriented architecture to enhance FEATURES p Comprehensive MIL-STD-1553 dual-redundant Bus p p p p p programmability p DMA memory interface with 64K addressability p Internal self-test p Radiation-hardened option available for 84-lead

SWBT13

Abstract: rta2 1553b rti
Contextual Info: UT1553B BCRT p Register-oriented architecture to enhance FEATURES p Comprehensive MIL-STD-1553B dual-redundant programmability p DMA memory interface with 64K addressability p Internal self-test p Remote terminal operations in ASD/ENASD-certified Bus Controller BC and Remote Terminal

fp6160

Abstract: rta2
Contextual Info: UT1553B BCRT p Register-oriented architecture to enhance FEATURES p Comprehensive MIL-STD-1553B dual-redundant programmability p DMA memory interface with 64K addressability p Internal self-test p Remote terminal operations in ASD/ENASD-certified Bus Controller BC and Remote Terminal

marking code H02

Abstract: CHN 455 Hitachi DSA002720
Contextual Info: SH7065 Hardware Manual ADE-602-166 Rev. 1.0 8/25/99 Hitachi, Ltd. Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in

STP2016

Abstract: SuperSPARC mbus 10 application STP2011 STP2016QFP mbus MCLK11 MOSC STP2012
Contextual Info: STP2016 July 1997 Clock-2 Generator System Clock Generator DATA SHEET DESCRIPTION The STP2016 Clock-2 Chip generates clock signals for components on the SBus and MBus. The MBus and SBus are used by SPARC processors, such as SuperSPARC™. The MBus is designed for multiprocessing MP , operating at

BCRT-30

Abstract: 12MHZ 1553B UT1553B MIL-STD-1553B D1398
Contextual Info: UT1553B BCRT ❐ DMA or pseudo-dual-port memory interface with FEATURES ❐ Comprehensive MIL-STD-1553B dual-redundant ❐ ❐ ❐ ❐ 64K addressability ❐ Internal wraparound self-test ❐ Time tagging and message logging in RT mode ❐ Packaged in 84-pin pingrid array, 84-lead flatpack, or

F10116

Abstract: rta2 12MHZ UT1553B mil-std-1553b SPECIFICATION BCRT-26 mil std 1553b MIL-STD-1773 UTMC
Contextual Info: UT1553B BCRT p Register-oriented architecture to enhance FEATURES p Comprehensive MIL-STD-1553B dual-redundant programmability p DMA memory interface with 64K addressability p Internal self-test p Remote terminal operations in ASD/ENASD-certified Bus Controller BC and Remote Terminal

LQFP28

Abstract: ed1321 AS1 P25 ATR2740 BGA121 D232 LQFP128 analog devices AD DAB I2111 dab circuitry
Contextual Info: Features • Highly Integrated Digital Device for DAB Receivers Eureka 147 • Utilizes the ARM7TDMI Core • • • • • • • • • • • • • • • – High-performance 32-bit RISC Architecture – High-density 16-bit Instruction Set

msi motherboard circuit diagram

Abstract: MSI MOTHERBOARD schematic diagram MSI MOTHERBOARD SERVICE MANUAL amd MOTHERBOARD SERVICE MANUAL L64811 circuit diagram of msi motherboard MOTHERBOARD msi CIRCUIT diagram intel D102 motherboard sparkit-40 l64863
Contextual Info: • 5304A04 LSI LOGIC 0013137 531 El LLC 53D4AD4 001313A 47fl LLC LSI Logic has derived the material in this manual, which describes the L64863 Clock Chip, from documents provided by Sun Microsystems, Inc. The chip described in this manual is guaranteed to function as described only when

mbus 10 application

Abstract: STP2012 TP2018
Contextual Info: S un M icroelectronics July 1997 Clock-2 Generator DATA SHEET System Clock Generator D e s c r ip t io n The STP2016 Clock-2 Chip generates clock signals for components on the SBus and MBus. The MBus and SBus are used by SPARC processors, such as SuperSPARC™. The MBus is designed for multiprocessing

STP201

Contextual Info: SPA RC T echrdogy Business N ovem ber 1994 S T P 2016 DATA SHEET D C lo c k s G e n e ra to r escription The STP2016 Clock-2 Chip generates clock signals for components on the SBus and MBus. The MBus and SBus are used by SPARC processors, such as SuperSPARC™. The MBus is designed for multi­

CSI 2702 alarm

Abstract: MR891 AC supply Terminal Consist of OTTA 6 SBC24 stk 077 amplifier
Contextual Info: R O C K W E L L S E M I C O N D U C T O R S Y S T E M S RS8398 Octal T l/El Framer PROVIDING HIGH SPEED MULTIMEDIA CONNECTIONS Advance Information This document contains information on a product under development. The parametric information contains target parameters that are subject to change.

BT8370KPF

Abstract: BT8370 Bt8370EVM MC68302 user
Contextual Info: Fully I n t e g r a t e d T l / E l F r a me r and Line I n t e r f a c e R O C K S00266 N8370DSE July 1 ,1 9 9 9 C O N E X A N T What's next in communications technologies C O M C X A N T B t8 3 7 0 /8 3 7 5 /8 3 7 6 Fully Integrated T l/E l Framer and Line Interface

A3818

Abstract: A5232 A5690 UT1553 McDonnell standards 1553L
Contextual Info: UT1553 BCRTMP ❐ ❐ ❐ ❐ FEATURES Time tagging and message logging in RT mode Packaged in 144-pin pingrid array, 132-lead flatpack Low-power CMOS technology Full military operating temperature range, -55°C to +125°C, screened to the specific test methods listed

TI 046 fRam

Contextual Info: C O N E X A N T BI8370/8375/8376 Fully Integrated T l/E l Framer and Line Interface The Bt8370/8375/8376 is a family of single chip transceivers for T1/E1 and Integrated Service Digital Network ISDN primary rate interfaces, operating at 1.544 Mbps or 2.048 Mbps. These devices combine a sophisticated framer, transmit and receive slip

Hitachi DSA00276

Abstract: chn 526
Contextual Info: Hitachi SuperH RISC engine SH7065 Hardware Manual ADE-602-166B Rev. 3.0 3/22/2001 Hitachi, Ltd. Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in

Contextual Info: ART Product Specification Sheet 1053N2 Initial Use dacs iv, dDM2000 Multiplexer Description 88 64 The 1053N2/409BP Multiplexer is designed for the DACS IV and DDM2000 digital multiplexer systems. In the DACS IV application, it provides a 27.8 MHz interface between 14 DSi rate signals and the DS1

hd6437065a

Abstract: CHN T4 1060 HC00A MSTAR SH7065F SH7000 SH7065 SH7065A japan servo co DME 10PE1
Contextual Info: To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid

CHN 703

Abstract: hd6437065a 8062 115c CHN 618 chn 637 chn 808 diode sy 166 850 nm LED TAD32 SH2-DSP programming manual
Contextual Info: SH7065 Hardware Manual ADE-602-166A Rev. 2.0 6/23/2000 Hitachi, Ltd. Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in

UT1553BCRTM

Abstract: 265u 11TA31 UT1553 UT1553B rta2
Contextual Info: UT1553 BCRTM ❐ DMA or pseudo-dual-port memory interface with FEATURES ❐ Comprehensive MIL-STD-1553 dual-redundant Bus ❐ ❐ ❐ ❐ 64K addressability ❐ Internal wraparound self-test ❐ Time tagging and message logging in RT and M modes ❐ Packaged in 84-pin pingrid array, 84-lead flatpack, or

sbi4.2

Abstract: sf 128d CSI 2702 alarm Technical Product RBS 3106 rbs 3106 Technical Product lm 398- SAMPLE AND HOLD siemens fl 232 v7 RBS 3106 CN8394KTF ETS300
Contextual Info: Preliminary Information This document contains information on a product under development. The parametric information contains target parameters that are subject to change. C O N E X A N T ' CN 8394/8395/8398 Quad/xl 6/Octal—T1/E1/J1 Framers The CN8394/8395/8398 is a family of single chip multiple framers for T1/E1/J1 and

TAD-32

Abstract: SH7065F hd6437065a CHN T4 1060 CHN 703 ceramic resonator CDB c28 CHN 618 HD64F7065A HD64F7065S SH7065
Contextual Info: To all our customers Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp. The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog

Contextual Info: STP2016 S un M ic r o e l e c t r o n ic s J u ly 1 9 9 7 Clock-2 Generator System Clock Generator DATA SHEET D e s c r ip t io n The STP2016 Clock-2 Chip generates clock signals for com ponents on the SBus and MBus. The M Bus and SBus are used by SPARC processors, such as SuperSPARC™. The M Bus is designed for multiprocessing

cmo 765

Abstract: SH2-DSP programming manual j 5804 SH7065f CHN T4 1060 HD6437065A ceramic resonator CDB c28 CHN 623 Diodes dmx servo pd26 do 214
Contextual Info: REJ09B0332-0500 The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. SH7065 32 Hardware Manual Renesas 32-Bit RISC Microcomputer