84LEAD Search Results

DOCUMENTATION OF SHADOW ALARM

Abstract: ndf 020-21
Contextual Info: T1Mx28 Device DS1 Mapper 28-Channel TXC-04228 TECHNICAL OVERVIEW PRODUCT PREVIEW FEATURES DESCRIPTION • Twenty-eight independent 1.544 Mbit/s DS1 mappers • Single/dual byte-parallel Telecom Bus @ 6.48 MHz 28 slots or 19.44 MHz (84 slots) • Floating VT1.5 byte-synchronous mapping for use

Contextual Info: STP2021 S un M ic r o e l e c t r o n ic s J u ly 1997 PMC Power Management Controller DATA SHEET D e s c r ip t io n The STP2021 Power Management Controller brings power management to SBus-based systems. The STP2021 interfaces to the SBus via the byte-wide expansion bus EBus provided by the STP2001 Slave I/O Controller.

80960SA

Abstract: 80960SB 65A176 AD427
Contextual Info: 80960SA EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • High-Performance Embedded ■ Pin Compatible with 80960SB Architecture — 20 MIPS* Burst Execution at 20 MHz — 7.5 MIPS Sustained Execution at 20 MHz ■ 512-Byte On-Chip Instruction Cache

vp44

Abstract: CY37064 CY37064V
Contextual Info: «oaHaoooiMMMWfMMMMMM!9:^ v’*'» -^ jjÉBT * ¿f5 ’00“’'* '^ 7“T{• < 1; .r - - •■■■■■■ c PRELIMINARY CY37064V 3, £ ,.* k v / k J UltraLogic 3.3V 64-Macrocell ISR™CLPD — tPD = 8.5ns Features — ts = 5.0 ns • 64 macrocells in four logic blocks

cy37128

Abstract: CY37128P160-125AC CY37128V CY7C375 CY37128P84-125JI cy3700
Contextual Info: = m m m !Æ '^ r ^ r : c Q CY3 7 1 2 8 PR £um A ^Y UltraLogic 128-Macrocell ISR™ CPLD — tco = 4.0 ns Features • • • • • • • • • • • 128 macrocells in eight logic blocks • In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming

CY101E383

Abstract: E383 99s1
Contextual Info: fax id: 5000 ,.V.Ï.Ï.V.^ y nr' Æ C Y 101E383 CYPRESS ECL/TTL/ECL Translator and High-Speed Bus Driver Features • BiCMOS for optimum speed/power • High speed max. — 2.5 ns tpQ TTL-to-ECL — 3 ns tpQ ECL-to-TTL Low skew < ± 1 ns Can operate on single +5V supply

UNITED TECHNOLOGIES MICROELECTRONICS CENTER

Contextual Info: Military Standard Products UT 1553 RTMP Remote Terminal Multi-Protocol Product Brief UNITED TECHNOLOGIES MICROELECTRONICS CENTER April 1988 FEATURES □ □ All h a n d sh a k in g signals p ro v id e d for D M A m em ory access im p lem en tatio n C om plete M IL -S T D -1 5 5 3 re m o te term in al

84 PIN CERAMIC QUAD FLAT PACK

Abstract: 2600 corning cypress flash 370 7C374-100 7C374-66 7C374L-66 CY7C373 CY7C374 FLASH370 CY7C374-83GC
Contextual Info: fax id: 6129 —— — - = : ! W Æ j r I 1 CY7C374 17 Q Q IT C O O UltraLogic 128-Macrocell Flash CPLD Features The logic blocks in the FLASH370 architecture are connected with an extremely fast and predictable routing resource— the Programmable Interconnect Matrix PIM . The PIM brings flex­

RS-343-A

Abstract: RS-343A BT458
Contextual Info: ADVANCED MICRO DEVICES *ÌL> D È | DSS7S5S 00203^5 1 Am81C81/Am81C82 • 28365 D T-SZ -33 - 09 CMOS Color Palette a ADVANCE INFORMATION > 3 co DISTINCTIVE CHARACTERISTICS Am81C81 On-chip phase-k>d<ed loop eliminates the need for ECL on PC board On-chip video timing generator

Contextual Info: Reflow Soldering Guidelines f o r S u r f a c e - M o u n t D e v ic e s Application Note 81 June 1996, ver. 1 Introduction A ltera's su rface-m ou n t prod u cts in clu d e quad flat p ack Q FP , J-lead chip carrier (JLC C and P LC C ), ball-g rid array (B G A ), and sm all-ou tlin e

bms 16s

Abstract: SWBT13 UT1553BCRTM ta306
Contextual Info: UT1553 BCRTM p Register-oriented architecture to enhance FEATURES p Comprehensive MIL-STD-1553 dual-redundant Bus p p p p p programmability p DMA memory interface with 64K addressability p Internal self-test p Radiation-hardened option available for 84-lead

SWBT13

Abstract: rta2 1553b rti
Contextual Info: UT1553B BCRT p Register-oriented architecture to enhance FEATURES p Comprehensive MIL-STD-1553B dual-redundant programmability p DMA memory interface with 64K addressability p Internal self-test p Remote terminal operations in ASD/ENASD-certified Bus Controller BC and Remote Terminal

fp6160

Abstract: rta2
Contextual Info: UT1553B BCRT p Register-oriented architecture to enhance FEATURES p Comprehensive MIL-STD-1553B dual-redundant programmability p DMA memory interface with 64K addressability p Internal self-test p Remote terminal operations in ASD/ENASD-certified Bus Controller BC and Remote Terminal

common mode rejection ratio test 1553B

Abstract: rta2 1553 SUmmit
Contextual Info: 1.0 INTRODUCTION The monolithic SµMMIT provides the system designer with an intelligent solution to MIL-STD-1553 multiplexed serial data bus design problems. The SµMMIT is a single-chip device that implements all three of the defined MIL-STD-1553 functions Remote Terminal, Bus Controller, and Monitor. Operating either

Contextual Info: 87C196CA/87C196CB 20 MHz ADVANCED 16-BIT CHMOS MICROCONTROLLER WITH INTEGRATED CAN 2.0 Automotive m High Performance CHMOS 16-Bit CPU • Full Duplex Synchronous Serial I/O Port SSIO (up to 20 MHz Operation) ■ Register-Register Architecture ■ Up to 56 Kbytes of On-Chip EPROM

Contextual Info: in tj 80960SB EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • High-Performance Embedded Architecture — 16 MIPS* Burst Execution at 16 MHz — 5 MIPS Sustained Execution at 16 MHz ■ Built-In Interrupt Controller — 4 Direct Interrupt Pins

Contextual Info: in te l 8XC196MC INDUSTRIAL MOTOR CONTROL MICROCONTROLLER 87C196MC 16 Kbytes of On-Chip OTPROM* 83C196MC 16 Kbytes of On-Chip ROM High Performance CHMOS 16-Bit CPU 16 Kbytes of On-Chip OTPROM/ROM 488 bytes of On-Chip Register RAM Register to Register Architecture

84-PIN

Abstract: CY7C341B
Contextual Info: CY7C341B y CYPRESS Features • 192 macrocells in 12 LABs • 8 dedicated inputs, 64 bidirectional I/O pin • Advanced 0.65-micron CMOS technology to increase performance • Programmable interconnect array • 384 expander product terms • Available in 84-pin HLCC, PLCC, and

DS51140

Abstract: DS51298 PIC32 PICC-18 44-pin plcc pcb mount footprint 44L PLCC socket XLT18SO-1
Contextual Info: Transition Socket Specification  2010 Microchip Technology Inc. DS51194S Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. •

Ultra37064

Abstract: CERAMIC LEADLESS CHIP CARRIER CY7C372 CY7C373 ieee1149.1 cypress
Contextual Info: J ^ m n rn n : if : Y PRELIMINARY H Ultra37064 - UltraLogic 64-Macrocell ISR™ CPLD Features — ts = 3.5 ns — tc o = 4.5 ns • 64 m a cro cells in fo u r logic blocks • P ro d uct-term clocking • In-S ystem R ep ro g ra m m ab le ™ IS R ™

MX 0541

Abstract: mx 0541 b CY7C373
Contextual Info: fax id: 6138 CY7C373Ì CYPRESS UltraLogic 64-Macrocell Flash CPLD Functional Description Features • 64 m a cro cells in fo u r logic blocks The C Y 7 C 3 73i is an In-System R eprogram m able C om plex P rogram m able Logic Device CPLD and is pa rt of the

K12J

Abstract: 100-PIN CY7C346 CY7C346B f 7400
Contextual Info: CY7C346 CY7C346B 5T CYPRESS 128-Macrocell MAX EPLDs Features Functional Description • 128 macrocells in 8 LABs • 20 dedicated inputs, up to 64 bidirec­ tional I/O pins • Programmable interconnect array • 0.8-micron double-metal CMOS EPROM technology CY7C346

NSf39

Abstract: IR 0251 CY7C024 CY7C0241 CY7C025 CY7C0251 017L
Contextual Info: fax id: 5206 CY7C024/0241 CY7C025/0251 4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int, Busy Features Functional Description • True D u al-P o rted m em o ry ce lls w h ich allow s im u ltan eo u s reads of th e s a m e m e m o ry location • 4K x 16 o rg an iza tio n C Y 7 C 02 4

CY101E383

Abstract: E383 E1472
Contextual Info: fax id: 5000 i , *" : :V:V:V:V:V:g:-v- : : ^ :^ ; ^3»* i ; : M m : M : i : m : CY101E383 ECL/TTL/ECL Translator and High-Speed Bus Driver Features • BiCMOS for optimum speed/power • High speed max. — 3.0 ns tpQ TTL-to-ECL — 4 ns tpQ ECL-to-TTL