ST ZD 125 Search Results

IHA910

Abstract: octal optocoupler ZD 260
Contextual Info: LID EIGHT CHANNEL VOLTAGE MONITORING OPTOCOUPLER MODULE WITH TRI-STATE BUFFERED OUTPUT ju o u tuu jjpji Devices supplied have completed rigorous testing, and various high reliability test options are offered. As manufacturer of high reliability optocouplers

Contextual Info: IS42G32256_ 256K x 32 x 2 16-Mbit SYNCHRONOUS GRAPHICS RAM ADVANCE INFORMATION APRIL 1998 FEATURES • Operating frequency: 125 MHz • 256,144 words x 32 bits x 2-bank organization • Programmable special register - Graphic cycles • Dual internal bank control

Contextual Info: Z9104 Variable Delay Motherboard Clock Buffer Preliminary PRODUCT FEA TURES • ■ ■ ■ ■ ■ ■ ■ ■ ■ Output phase relationship is precisely controllable with respect to input clock via a dedicated external feedback path. 6 Low Skew Clocks Generated

Contextual Info: f i l i Z9104 IH rJli v H I H « • '* i i s f isa W Variable Delay Motherboard Clock Buffer Preliminary PRODUCT FEA TURES • ■ ■ ■ ■ ■ ■ ■ ■ ■ Output phase relationship is precisely controllable with respect to input clock via a dedicated external feedback path.

Contextual Info: Z9102 Variable Delay Motherboard Clock Buffer Approved Product PRODUCT FEA TURES • ■ ■ ■ ■ ■ ■ ■ ■ Output phase relationship is precisely controllable with respect to input clock via a dedicated external feedback path. 6 Low Skew Clocks Generated

Contextual Info: MM! Z9102 mñMi Variable Delay Motherboard Clock Buffer Approved Product PRODUCT FEA TURES • ■ ■ ■ ■ ■ ■ ■ ■ Output phase relationship is precisely controllable with respect to input clock via a dedicated external feedback path. 6 Low Skew Clocks Generated

Contextual Info: Z9102 Fï Variable Delay Motherboard Clock Buffer Approved Product PRODUCT FEA TURES • ■ ■ ■ ■ ■ ■ ■ ■ Output phase relationship is precisely controllable with respect to input clock via a dedicated external feedback path. 6 Low Skew Clocks Generated

Contextual Info: L7C162 16K x 4 Static R A M FEATURES □ 16K x 4 Static RAM with Separate I/O and High Impedance Write □ Auto-Powerdown Design □ Advanced CMOS Technology □ High Speed — to 12 ns maximum □ Low Power Operation Active: 325 mW typical at 25 ns Standby: 400 [iW typical

Contextual Info: HN58V65A Series HN58V66A Series 8192-word x 8-bit Electrically Erasable and Programmable CMOS ROM HITACHI ADE-203-539A Z Rev. 1.0 Aug. 28, 1997 Description The Hitachi HN58V65A series and HN58V66A series are a electrically erasable and programmable EEPROM’s organized as 8192-word x 8-bit. They have realized high speed, low power consumption and

mb88625b

Abstract: MB88625B-PF MBM27C256A-25CZ D64001S-3C P Channel Equivalent to buz 350 MBM27C256A-25CV MB88625B-PSH pa2al MB886 GD03
Contextual Info: FUJITSU LTD S3E D m 3 7 4 cì75fc. GD03131 bOQ * F C A J cP June 1992 E m h n 1 -° T _ DATA SHEET = = = - FUJITSU / F2MCB-4L FAMILY MB88620B SERIES SINGLE CHIP MICROCONTROLLER WITH ADC AND VFD DRIVER DESCRIPTION The Fujitsu MB88620B Seríes is a member of the F2M C -4L Family, and features a 26

Contextual Info: L7C164/166 16K x 4 Static R A M FEATURES DESCRIPTION □ 16K x 4 Static RAM with Common I/O □ Auto-Powerdown Design □ Advanced CMOS Technology □ High Speed — to 12 ns maximum □ Low Power Operation Active: 325 mW typical at 25 ns Standby: 400 iW typical

Contextual Info: L 7 C 1 9 4 /1 9 5 64K x 4 Static RAM D E V IC E S IN C O R P O R A T E D DESCRIPTION FEATURES □ 64K x 4 Static RAM with Common I/O □ Auto-Powerdown Design □ Advanced CMOS Technology □ High Speed — to 15 ns maximum □ Low Power Operation Active: 210 mW typical at 35 ns

Contextual Info: L7C164/166 \}\v s DESCRIPTION FEATURES □ 16K x 4 Static RAM with Common I/O □ Auto-Powerdown Design □ Advanced CMOS Technology □ High Speed — to 12 ns maximum □ Low Power Operation Active: 325 mW typical at 25 ns Standby: 400 |iW typical □ Data Retention at 2 V for Battery

Contextual Info: MX23C1 611 16M-BIT MASK ROM 8/16 BIT OUTPUT FEATURES ORDER INFORMATION • Bit organization - 2M x 8 (byte mode) - 1M x 16 (word mode) • Fast access time - Random access: 100ns (max.) - Page access: 50ns (max.) • Page Size - 8 double words per page • Current

Contextual Info: 8 Megabit CMOS SRAM M I C R O S Y S T E MS DPS1MS8MP DESCRIPTION: The D PS1M S8M P is a 1Meg x 6 high-density, low-power static RAM module comprised of two 512K x 8 monolithic SRAM's, an advanced high-speed CMOS decoder and decoupling capacitors surface mounted on

ES981

Abstract: WAVETABLE
Contextual Info: ESS Technology, Inc. ES690 Wavetable Music Synthesizer Product Brief DESCRIPTION FEATURES The ES690 is a single, highly integrated, high-performance, and economical wavetable music synthesizer for personal computers, delivering superior acoustic sound comparable to expensive

DP-64S

Abstract: FP-80B HD81901 HD81901CPS2 HD81901FS2 HD81901PS2 V27bis D2738 d2144
Contextual Info: HD81901 -Single Chip Modem Supporting V.27ter/bis and V.26/bis Description The HD81901 is a single chip CMOS LSI modem based on the CCITT V.27ter/bis and V.26/bis stan­ dards. It can be used in the All Japan Bank network protocol, in the JCA protocol, and in JUST-PC, PC,

B047

Abstract: L162 V7-1A27D8-207
Contextual Info: CATALOG MICRO SWITCH F E D .M F G .C O D E V 7 -1 A 2 7 D 8 -2 0 7 SW ITCH-BASIC a Honeywell Division L I ST ING C W -B 0470 9 1929 .385 .125 CM 00 1 CN .187 * .0 0 3 a •> 00 T o on CL CN < CORROSION RESISTANT STEEL ACTUATOR > - 0 .19 X .19 WIDE OIL BRONZE ROLLER

Contextual Info: HD81901 -Single Chip Modem Supporting V.27ter/bis and V.26/bis Description The HD81901 is a single chip CMOS LSI modem based on the CCITT V.27ter/bis and V.26/bis stan­ dards. It can be used in the All Japan Bank network protocol, in the JCA protocol, and in JUST-PC, PC,

Contextual Info: M O TO R O LA SEMICONDUCTOR TECHNICAL DATA Order this docum ent by MCM69P618A/D MCM69P618A Product Preview 64K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM The MCM69P618A is a 1M bit synchronous fast static RAM designed to pro­ vide a burstable, high performance, secondary cache for the 68K Family, Pow­

Contextual Info: Paradigm PDM44036 32K x 36 Fast CMOS Synchronous Static SRAM with Linear Burst Counter Features Description n Interfaces directly with the Motorola 680X0 and PowerPC processors 80,66, 60, 50,40 MHz □ High Speed Access Times - Clock to data valid times:

Contextual Info: L7C162 16K x 4 Static RAM DEVICES INCORPORATED FEATURES DESCRIPTION □ 16K x 4 Static RAM with Separate I /O and High Impedance Write The L7C162 is a high-performance, low-power CMOS static RAM. The storage cells are organized as 16,384 words by 4 bits per word. Data In and

cnz916

Abstract: 5242C LX5241CDB LX5241CPW LX5241CTF LX5242CDB LX5242CPW LX5242CTF zd 4.1
Contextual Info: LIN Doc #: UltraWMUr LX5241/5242 M ultimode T H I n f i n i t e P o w e r I n n o v a t i o n o f 52 4 1 SCSI P r e l i m i n a r y DESCRIPTION T erm inator D ata S h e e t KEY FEATURES T h e L X 5 2 4 1 /4 2 is a m u ltim o d e SCSI term in ato r is tied to th e D IFFSE N SE in p u t o f th e c o rre ­

Contextual Info: IM P5241/42 9 -Lin e M ultim ode LV D /SE S C S I Term in ato r ISO 9001 Registered K E Y FEATURES D ESCR IPTIO N The IMP5241/42 is a multimode SCSI terminator that conforms to the SCSI Parallel Interconnect2 SPI-2 specification developed by the T10 standards committee for low voltage differential