vhdl code for ARINC
Abstract: arinc 429 serial transmitter verilog code for 8 bit fifo register DD-03182 vhdl code for rs232 receiver vhdl code for rs232 receiver using fpga asynchronous fifo vhdl KEYPAD 4 X 4 verilog ARINC DEI1070
Contextual Info: ARINC 429 Bus Interface Product Summary Core Deliverables • – Intended Use • ARINC 429 Transmitter Tx • ARINC 429 Receiver (Rx) Evaluation Version • Netlist Version – Key Features • Compiled RTL Simulation Model, Compliant with the Actel Libero Integrated Design
|
Original
|
vhdl code for arincarinc 429 serial transmitterverilog code for 8 bit fifo registerdd-03182+6vhdl code for rs232 receivervhdl code for rs232 receiver using fpgaasynchronous fifo vhdlkeypad 4 x 4 verilogarincdei1070
|
PDF
|
rg82855pm
Abstract: RG82855PM 855PM SL752 subwoofer preamp diagram SL752 Intel RG82855pm wistron BC547 audio WISTRON power sequence Intel 855PM Odem ICH4-M B220LFA
Contextual Info: Mobil CPU Banias uFCPGA CRT TV OUT 16 CARDBUS & 1394 TI 4510 ATI M10-CSP64 LVDS LCD 12 VGA 16 dual channel 31 LAN L4:VCC L5:Signal 2 L6:GND L7:Signal 3 L8:Component ATA 66/100 left side ICH4-M RTL 8101L PRIMARY IDE 3/5V DC/DC TXFM 17,18,19 USB2.0 PORT*3
|
Original
|
m10-csp6466mhz400mhz855pm+15266/333mhz44k0133mhz11b/a8101lrg82855pmrg82855pm 855pm sl752subwoofer preamp diagramsl752intel rg82855pmwistronbc547 audiowistron power sequenceintel 855pm odem ich4-mb220lfa
|
PDF
|
RTL code for ethernet
Abstract: IXB8055 IXF440 IXP1200
Contextual Info: Intel IXB8055 UTOPIA/POS Reference Design Hardware Validation April 2001 Order Number: 278379-002 Revision History Date Revision Description 3/19/01 001 First release. 4/13/01 002 Update trademark and copyright usage. No technical changes. Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual
|
Original
|
ixb805532-bit-mode16-bit-modertl code for ethernet+2ixf440ixp1200
|
PDF
|
4588c
Abstract: MEGA 8515 451c data sheet str 6307 str 6307 datasheet Edison time delay
Contextual Info: TC240 Boosts Systems-on-a-Chip Integration Increasing Need for System Chips The race is on among electronics manufacturers to roll out multimedia products that capture and present information in a combination of text, graphics, video, animation, and sound. Multimedia chips demand ever
|
Original
|
tc2404588cmega 8515451c+3data sheet str 6307str 6307 datasheetedison time delay
|
PDF
|
rtl nand gate
Abstract: TC240C MEGA 8515 str 6307 datasheet STR 6307 POWER TC220C TC240 Edison time delay BGA90 BGA900
Contextual Info: TC240 Boosts Systems-on-a-Chip Integration Increasing Need for System Chips The race is on among electronics manufacturers to roll out multimedia products that capture and present information in a combination of text, graphics, video, animation, and sound. Multimedia chips demand ever
|
Original
|
tc240rtl nand gatetc240cmega 8515+6str 6307 datasheetstr 6307 powertc220cedison time delaybga90bga900
|
PDF
|
|
Contextual Info: Sharing External Memory Bandwidth Using the Multi-Port Front-End Reference Design AN-637-01 Application Note This document describes the features and architecture of the Altera Multi-Port Front-End MPFE reference design, details the design flow you should follow to
|
Original
|
an-637-01 |
PDF
|
Soft Core RTL USB
Abstract: microelectronics ASIC USB 2.0 coach 12 Shenzhen State Microelectronics UDC20 RTL 604 GDS VCI
Contextual Info: Standard Bus IP: High Speed USB 2.0 Device Controller Fujitsu Macro F_USB20LP LINK PHY CPU Fujitsu USB 2.0 device controller is a synthesizable core suitable for different process. Corresponding physical interface in 0.18um and 0.11um technology supporting high and full speed operation
|
Original
|
usb20lpsoft core rtl usbmicroelectronicsasic usb 2.0+5coach 12shenzhen state microelectronicsudc20rtl 604gds vci
|
PDF
|
vhdl code for ARINC
Abstract: DD-03182 DEI1070 GPS clock code using VHDL ARINC arinc 429 serial transmitter verilog code for apb APA075 APA750 AX125
Contextual Info: Core429_APB v3.0 Handbook Actel Corporation, Mountain View, CA 94043 2008 Actel Corporation. All rights reserved. Printed in the United States of America Part Number: 50200096-2 Release: January 2008 No part of this document may be copied or reproduced in any form or by any means without prior written
|
Original
|
core429vhdl code for arincdd-03182dei1070+7gps clock code using vhdlarincarinc 429 serial transmitterverilog code for apbapa075apa750ax125
|
PDF
|
A2F500M3G
Abstract: vhdl code for ARINC GPS clock code using VHDL 32 bit cpu verilog testbench A2F500M ARINC 664
Contextual Info: Core429_APB v3.4 Handbook Core429_APB v3.4 Handbook Table of Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
|
Original
|
core429a2f500m3gvhdl code for arincgps clock code using vhdl+332 bit cpu verilog testbencha2f500marinc 664
|
PDF
|
verilog code for dpd
Abstract: wimax OFDMA Matlab code OFDMA Matlab code OFDM FFT verilog code for FFT 32 point vhdl code for FFT 32 point vhdl cyclic prefix code carrier frequency offset estimation 2C35 2S30
Contextual Info: Uplink Desubchannelization for WiMAX Application Note 450 February 2007, version 1.0 Introduction Altera provides building blocks to accelerate the development of a worldwide interoperability for microwave access WiMAX compliant basestations. This application note describes a reference design that
|
Original
|
16e-2005verilog code for dpdwimax ofdma matlab codeofdma matlab code+7ofdm fftverilog code for fft 32 pointvhdl code for fft 32 pointvhdl cyclic prefix codecarrier frequency offset estimation2c352s30
|
PDF
|
STK 2028
Abstract: RTL 2832 STK 4133 II gc 7137 ad STK 5333 stk 5392 stk 5490 stk 2265 STK 5474 STK 4197
Contextual Info: Mon Feb 6 10:03:42 1995 Page 1 'MENSCH COMPUTER ROM SOFTWARE' 'IRQVCTRS.ASM-IRQ VECTOR EQUATES FOR WDC65C265' 2500 A.D. 65816 Macro Assembler - Version 5.01g -Input Filename : irom2.asm Output Filename : irom2.obj
|
Original
|
wdc65c265stk 2028rtl 2832stk 4133 ii+7gc 7137 adstk 5333stk 5392stk 5490stk 2265stk 5474stk 4197
|
PDF
|
flash controller verilog code
Abstract: MT41J64M16LA-187E sodimm ddr3 connector PCB footprint DDR3 sodimm pcb layout micron ddr3 DDR3 pcb layout "DDR3 SDRAM" temperature controller using microcontroller ddr3 Designs guide DDR2 pcb layout
Contextual Info: External Memory Interface Handbook Volume 6: Design Tutorials 101 Innovation Drive San Jose, CA 95134 www.altera.com EMI_TUT-2.0 1 Document Version: Document Date: 2.0 July 2010 Copyright 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other
|
Original
|
flash controller verilog codemt41j64m16la-187esodimm ddr3 connector pcb footprintddr3 sodimm pcb layout+6micron ddr3ddr3 pcb layoutddr3 sdramtemperature controller using microcontrollerddr3 designs guideddr2 pcb layout
|
PDF
|
transistor k702
Abstract: transistor k703 transistor k79 transistor k215 TRANSISTOR K550 K206 transistor Transistor k822 CN701 transistor k620 transistor k230
Contextual Info: ORDER NO. CPD0603076C0 Notebook Computer CF-18 This is the Service Manual for the following areas. Z …for PCPE /CPE Model No. CF-18JHUZBZZ 2006 Matsushita Electric Industrial Co., Ltd. All rights reserved. Unauthorized copying and distribution is a violation of law.
|
Original
|
cpd0603076c0cf-18cf-18jhuzbzzk1mn04b00073+15k1ka07ba0014c0ebh0000457c1db00001351xp0431200lunr9113j0ltransistor k702transistor k703transistor k79transistor k215transistor k550k206 transistortransistor k822cn701transistor k620transistor k230
|
PDF
|
439 b14
Abstract: 547 B38 037 B34 822 b10 547 B34 828 B34 xl 0840 datasheet MG73Q rtl 795 MSM13Q
Contextual Info: 0.35µm ASICs MSM13Q/14Q CBA Family Masterslices MSM13Q / 14Q Series I/O Pads Raw Gates Usable Gates [*] MSM13Q 3LM Usable Gates [*] MSM14Q (4LM) 0150 0230 0340 0530 0840 1020 144 176 208 256 320 352 157,192 242,400 346,176 536,400 847,048 1,033,000 105,319
|
Original
|
msm13q/14qmsm13qmsm14qmsm98q/99q+11msm98qmsm99q439 b14547 b38037 b34822 b10547 b34828 b34xl 0840 datasheetmg73qrtl 795
|
PDF
|
|
|
full subtractor implementation using NOR gate
Abstract: fpga based 16 QAM Transmitter for wimax application with quartus fpga based 16 QAM Transmitter for wimax application with matlab 256POINT vhdl code for rotation cordic WCDMA DUC CORDIC altera cordic sine cosine generator vhdl vhdl code for radix 2-2 parallel FFT for ofdm vhdl code for radix-4 fft
Contextual Info: DSP Builder Handbook Volume 3: DSP Builder Advanced Blockset 101 Innovation Drive San Jose, CA 95134 www.altera.com HB_DSPB_ADV-1.0 Document Version: Document Date: 1.0 June 2010 Copyright 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other
|
Original
|
full subtractor implementation using nor gatefpga based 16 qam transmitter for wimax application with quartusfpga based 16 qam transmitter for wimax application with matlab256point+6vhdl code for rotation cordicwcdma duccordic alteracordic sine cosine generator vhdlvhdl code for radix 2-2 parallel fft for ofdmvhdl code for radix-4 fft
|
PDF
|
MT41J64M16LA
Abstract: MT41J64M16LA-187E MT8HTF12864HDY-800G1 "DDR3 SDRAM" sodimm ddr3 connector PCB footprint DDR3 pcb layout MT41J64M16LA-15E MT41J64M16 DDR3 layout micron DDR3 SODIMM address mapping edge connector
Contextual Info: Section I. DDR, DDR2, and DDR3 SDRAM Design Tutorials 101 Innovation Drive San Jose, CA 95134 www.altera.com EMI_TUT_DDR-1.1 Document Version: Document Date: 1.1 February 2010 Copyright 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other
|
Original
|
mt41j64m16lamt41j64m16la-187emt8htf12864hdy-800g1ddr3 sdram+6sodimm ddr3 connector pcb footprintddr3 pcb layoutmt41j64m16la-15emt41j64m16ddr3 layoutmicron ddr3 sodimm address mapping edge connector
|
PDF
|
verilog code for implementation of des
Abstract: verilog code for des tsmc sram des verilog RTL 604
Contextual Info: FIPS 46-3 Standard Compliant DES Data Encryption Standard Core Encryption/Decryption performed in 16 cycles ECB mode 56 bits of security For use in FPGA or ASIC designs Verilog IP Core Non Pipelined version Small gate count The DES core implements the Data Encryption Standard (DES) documented in the U.S.
|
Original
|
0x0123456789abcdef0x4e6f7720697320740x68652074696d65200x666f7220616c6c20+80x3fa40e8a984d48150x6a271787ab8883f90x893d51ec4b563b53verilog code for implementation of desverilog code for destsmc sramdes verilogrtl 604
|
PDF
|
MT41J64M16LA-187E
Abstract: MT41J64M16LA MT8HTF12864HDY-800G1 design of dma controller using vhdl sodimm ddr3 connector PCB footprint DDR3 DIMM footprint ddr3 Designs guide micron ddr3 MT47H32M16CC-3 temperature controller using microcontroller
Contextual Info: Section I. ALTMEMPHY Design Tutorials 101 Innovation Drive San Jose, CA 95134 www.altera.com EMI_TUT_DDR-2.0 Document Version: Document Date: 2.0 July 2010 Copyright 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other
|
Original
|
mt41j64m16la-187emt41j64m16lamt8htf12864hdy-800g1design of dma controller using vhdl+6sodimm ddr3 connector pcb footprintddr3 dimm footprintddr3 designs guidemicron ddr3mt47h32m16cc-3temperature controller using microcontroller
|
PDF
|
Camera processors
Abstract: Zoran ZORAN CORPORATION CCIR-656
Contextual Info: Solutions CVE2 NTSC/PAL ENCODER CVE2 Product Brief Zoran Corporation 3112 Scott Boulevard Santa Clara, CA 95054-3317 on a Chip T e l 408.919.4 1 1 1 Fax 408.919.4122 www.zoran.com Core Features • • • • • • • • • Encodes YCrCb into NTSC or PAL/SECAM
|
Original
|
03/02-ldcamera processorszoranzoran corporation+1ccir-656
|
PDF
|
Zoran
Abstract: CCIR-656
Contextual Info: Driving the Digital Lifestyle CVE2 NTSC/PAL Video Encoder Product Brief DVD Zoran Corporation 1390 Kifer Road Sunnyvale, CA 94086-5305 Digital Camera Digital TV Imaging IP Cores Te l 408.523.6500 Fax 408.523.6501 www.zoran.com Description Zoran’s CVE2 NTSC/PAL video encoder core continues a line of
|
Original
|
7/16/04-tszoranccir-656 |
PDF
|
GENE-6310
Abstract: VIA VT8606 vt82c686b 36 dstn lcd tv lvds cable pin voltages 83977ef GENE-6310-B1001 VIA VT8606 dstn usb to 36 pin parallel connector Gene GENE-6310-B11-01 VIA VT8606
Contextual Info: GENE-6310 Rev.B Rev.B VIA C3 Low Power Processor Compa ct Features Onboard VIA C3™ Low Power Processor 18/36-bit Dual Channel LVDS/TTL TFT/DSTN LCD AC-97 High-quality Audio Subcom pact Supports Type II CompactFlash™ Memory 4 COM / 4 USB / TV-out Ports
|
Original
|
gene-631018/36-bitac-97udma33+14rs-232rs-232/422/485pci-104pc/104gene-6310b/6320/6330via vt8606 vt82c686b 36 dstnlcd tv lvds cable pin voltages83977efgene-6310-b1001via vt8606 dstnusb to 36 pin parallel connectorgenegene-6310-b11-01via vt8606
|
PDF
|
RTL 602 W
Abstract: IC802 transistor T1J K40 fet IC-221 CN602 transistor k38 w7 transistor k79 VC175 DFJP050ZA002
Contextual Info: ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! "#$%#!&"'! $*+*,*-(,! ! ./012341! (567893:! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! (;<),!
|
Original
|
i/08/465134b086c39e73b+14518d9i5134m0934n58d2bdrtl 602 wic802transistor t1jk40 fetic-221cn602transistor k38 w7transistor k79vc175dfjp050za002
|
PDF
|
asynchronous fifo vhdl
Abstract: 8 BIT ALU design with verilog/vhdl code full subtractor using ic 74138 74139 for bcd to excess 3 code vhdl code for 8bit bcd to seven segment display 32 BIT ALU design with verilog/vhdl code 74594 16 BIT ALU design with verilog/vhdl code B1516 RAM1024
Contextual Info: QuickWorks User Manual with SpDE Reference Release 2009.2.1 Contact Information QuickLogic Corporation 1277 Orleans Drive Sunnyvale, CA 94089 Phone: (408) 990-4000 (US) (905) 940-4149 (Canada) +(44) 1932-57-9011 (Europe) +(852) 2567-5441 (Asia) E-mail: info@quicklogic.com
|
Original
|
asynchronous fifo vhdl8 bit alu design with verilog/vhdl codefull subtractor using ic 7413874139 for bcd to excess 3 code+6vhdl code for 8bit bcd to seven segment display32 bit alu design with verilog/vhdl code7459416 bit alu design with verilog/vhdl codeb1516ram1024
|
PDF
|
CCIR-656
Abstract: pal sync generator CVE2
Contextual Info: CONNECT DVD SHARE E N T E R TA I N D I G I TA L C A M E R A CVE2 NTSC/PAL VIDEO ENCODER Product Brief D I G I TA L T V D I G I TA L P R I N T I N G MOBILE IP CORES Zoran Corporation 1390 Kifer Road Sunnyvale, CA 94086 408 523 6500 Fax 408 523 6501 www.zoran.com
|
Original
|
ccir-601ccir-656pal sync generatorcve2 |
PDF
|