REFRESH LOGIC Search Results

AS4LC4M4E1-60JC

Abstract: AS4LC4M4E1-50JC AS4LC4M4E1-50JI AS4LC4M4E1-50TC AS4LC4M4E1-50TI AS4LC4M4E1-60JI AS4LC4M4E1-60TC AS4LC4M4E1-60TI
Contextual Info: April 2001 AS4LC4M4E1 4Mx4 CMOS DRAM EDO 3.3V Family Features • Refresh - 2048 refresh cycles, 32 ms refresh interval - RAS-only or CAS-before-RAS refresh or self-refresh • TTL-compatible, three-state I/O • JEDEC standard package - 300 mil, 24/26-pin SOJ

AS4LC4M4F1-50JC

Abstract: AS4LC4M4F1-50JI AS4LC4M4F1-50TC AS4LC4M4F1-50TI AS4LC4M4F1-60JC AS4LC4M4F1-60JI AS4LC4M4F1-60TC
Contextual Info: May 2001 AS4LC4M4F1 4Mx4 CMOS DRAM Fast Page 3.3V Family Features • Refresh • Organization: 4,194,304 words × 4 bits • High speed - 2048 refresh cycles, 32 ms refresh interval - RAS-only or CAS-before-RAS refresh or self-refresh - 50/60 ns RAS access time

Contextual Info: AS4C256K16E0 5V 256Kx 16 CMOS DRAM EDO Features • Refresh - 5 1 2 refresh cycles, 8 m s refresh interval - RAS-only o r CAS-before-RAS refresh o r self-refresh - Self-refresh o p tio n is available for n e w g en eratio n device • O rganization: 2 6 2 ,1 4 4 w o rd s x 16 bits

RR 113001

Abstract: 1M16E5
Contextual Info: Advance information •■ AS4VC1M16E5 A 2.5V lM x 16 CMOS lntelliwatt,v DRAM EDO Features 1 1024 refresh cycles, 16 ms refresh interval • Organization: 1,048,576 words x 16 bits • High speed - RAS-only or CAS-before-RAS refresh or self refresh 1Read-modify-write

6E025

Contextual Info: Features • Refresh • O rganization: 262,144 w o rd s x 16 bits - 512 refresh cycles, 8 ms refresh interval • H ig h speed - 2 5 / 3 0 / 3 5 / 5 0 ns R A S access tim e - RA S-only o r CAS-before-RAS refresh o r self-refresh - 1 2 /1 6 /1 8 /2 5 ns co lu m n address access tim e

Contextual Info: Advance information •■ AS4SC1M 16E5 A 1,8V 1M x 16 C M O S Intelliwatt1'' DRAM EDO Features • Organization: 1,048,576 words x 16 bits • High speed • 1 0 2 4 refresh cycles, 16 m s refresh interval - RAS-only or CAS-before-RAS refresh or self refresh

Contextual Info: Advance information •■ AS4VC256K16E0 A 2.5V 256KX 16 CMOS DRAM EDO Features • 512 refresh cycles, 8 ms refresh interval • Organization: 262,144 w ords x 16 bits - RAS-only or CAS-before-RAS refresh or self refresh • H ig h speed - 45/60 ns KAS access tim e

13001 LZ

Abstract: SR 13001 PA 13001
Contextual Info: Advance information •■ II AS4VC1M16E5 2.5V 1Mx 16 CMOS lntelliwatt,v DRAM EDO Features • Organization: 1 ,0 4 8 ,5 7 6 w ords • H igh speed X • 10 24 refresh cycles, 16 m s refresh interval 16 bits - RAS-only or CAS-before-RAS refresh or self refresh

Contextual Info: AS4LC256K16E0 A 3.3V 2 5 6 K X 16 CMOS DRAM EDO Features • 5 1 2 refresh cycles, 8 m s refresh interval - RAS-only or CAS-before-RAS refresh or self refresh • Organization: 262,144 w ords x 16 bits • H igh speed - 3 5 / 4 5 / 6 0 ns K K access tim e

AM2964B

Abstract: 16-32K
Contextual Info: Am2964B Advanced Micro Devices Dynamic Memory Controller DISTINCTIVE CHARACTERISTICS Dynamic Memory Controller for 16K and 64K MOS dynamic RAMs 8 -Bit Refresh Counter for refresh address generation, has clear input and terminal count output Refresh Counter terminal count selectable at 256 or 128

4LCIM16E5-50

Abstract: 4LCIM16E5 4LC1M16E5 AS4LC1M16ES j130007a 4C1M16E5-60 AS4CIM16E5 j13000
Contextual Info: Preliminary information Features • 1024 refresh cycles, 16 ms refresh interval • Organization: 1,048,576 w ords x 16 bits • High speed - RAS-only or CAS-before-RAS refresh • Read-modify-write • TTL-compatible, three-state DQ • JEDEC standard package and pinout

Contextual Info: Il High Performance 256Kxl6 CMOS DRAM AS4C256K16F0 High Speed 256Kxl6 CMOS DRAM Fast Page Mode PRELIMINARY I F E A TU R E S_ • 512 refresh cycles, 8 ms refresh interval • Organization: 262,144 words by 16 bits - RAS-only or CAS-before-RAS refresh

Contextual Info: Signetics 2964B Dynamic Memory Controller Product Specification Logic Products FEATURES • Operating Options — controls 16K or 64K DRAMs • 8-Bit Refresh Counter — refresh address generation, clear input, and selectable terminal count 128 or 256 output

16f550

Abstract: 16F54
Contextual Info: A Advance information •■ AS4LC1M16F5 3.3V l M x 16 CM O S DRAM fast page mode Features • 1024 refresh cycles, 16 ms refresh interval • Organization: 1,048,576 words x 16 bits • High speed - KAS-only o r CAS-before-KAS refresh • Read-modify-write

EL01

Abstract: 964b 4KDRAM
Contextual Info: 2964B Signetics Dynamic Memory Controller Product Specification Logic Products FEATURES • Operating Options — controls 16K or 64K DRAMs • 8-Bit Refresh Counter — refresh address generation, clear input, and selectable terminal count 128 or 256 output

Decoder 8 to 256 single ic

Abstract: Dynamic Memory Controller
Contextual Info: Signetìcs 2964B Dynamic Memory Controller Product Specification Logic Products FEATURES • Operating Options — controls 16K or 64K DRAMs • 8-Bit Refresh Counter — refresh address generation, clear input, and selectable terminal count 128 or 256 output

Contextual Info: High Perform ance lM x 16 CMOS DRAM A S4C 1M 16E 5 1 M x 16 CMOS EDO DRAM Preliminary information Features • 1024 refresh cydes, 16 ms refresh interval • Organization: 1,048,576 words x 16 bits • High speed - RAS-only or CAS-before-RAS refresh • Read-modify-write

fopf

Abstract: ob35l0s a 3116 HYB3116160BSJ-50 HYB3116160BSJ-60 HYB3116160BSJ-70 HYB3118160BSJ-50 HYB3118160BSJ-60 HYB3118160BSJ-70 71ST5
Contextual Info: S IE M E N S 1M X 16-Bit Dynamic RAM 1 k & 4k-Refresh HYB 3116160BSJ-50/-60/-70 HYB 3118160BSJ-50/-60/-70 Advanced Inform ation Output unlatched at cycle end allows tw o ­ dim ensional chip selection Read, write, read-m odify-write, CAS-before-RAS refresh, RAS-only refresh,

c2m6b

Abstract: C2MF
Contextual Info: ADVANCE |viic: r MT4 L C2M8B1/2 S 2 MEG x 8 DRAM o n 2 MEG x 8 DRAM 5.0V SELF REFRESH (MT4C2M8B1/2 S) 3.0/3.3V, SELF REFRESH (MT4LC2M8B1/2 S) FEATURES PIN ASSIGNMENT (Top View) • SELF REFRESH, i.e. "Sleep M ode" • Industry standard x8 pinouts, tim ing, functions and

16F5

Abstract: 4c1m16
Contextual Info: Preliminary information Features • 1024 refresh cycles, 16 ms refresh interval • Organization: 1,048,576 words x 16 bits • High speed - 50/60 ns RAS access time - 20/25 ns fast page cycle time - 13/17 ns CAS access time • Low power consumption - RAS-only o r ¿AS-before-ftAS refresh

Contextual Info: High P erform ance 1MX4 CMOS DRAM H A S4C14405 Il IM X 4 C M 0 S EDO DRAM Preliminary information Features • 1024 refresh cydes, 16 ms refresh interva • Organization: 1,048,576 words x 4 bit • High speed - RAS-only o r CAi>-before-RAS refresh • Read-modify-write

1I-3Q006-A

Contextual Info: H i <; li IV !'t <>r ! 11.! r !M > • \io s D l: 4 Ii S A : M A l C M O S U Ù UK. , M Prelim inary inform ation Features • Organization: 1,048,576 words x 4 bits • High speed • 1024 refresh cycles, 16 ms refresh interval - RAS-only or CAS-before-RAS refresh

Contextual Info: MICRON SEMICONDUCTOR INC b3E D • blllSH^ □□□77A3 B4T « M R N ADVANCE MT4 L C2M8B1/2 S 2 MEG X 8 WIDE DRAM MICRON I SEMICONDUCTOR. INC WIDE DRAM 2 MEG X 8 DRAM 5.0V SELF REFRESH (MT4C2M8B1/2 S) 3.0/3.3V, SELF REFRESH (MT4LC2M8B1/2 S) FEATURES • SELF REFRESH, or "Sleep Mode"

Contextual Info: ADVANCE MT4 L C2M8B1/2 S 2 MEG x 8 DRAM I^ IC Z R O N 2 MEG x 8 DRAM 5.0V SELF REFRESH (MT4C2M8B1/2 S) 3.0/3.3V, SELF REFRESH (MT4LC2M8B1/2 S) FEATURES PIN ASSIGNMENT (Top View) • SELF REFRESH, i.e. "Sleep M ode" • Industry standard x8 pinouts, tim ing, functions and