S4C256K Search Results

AS4C256K16F0-60JC

Abstract: 1j30 AS4C256K16F0 AS4C256K16F0-60 1J3000
Contextual Info: H ig h P e rfo rm a n c e 256K.X 16 CMOS DRAM H A S4C256K 16F0 A H ia h Speed 2 5 6 K X 1 6 CMOS DRAM F a st p a g e m ode Prelim inary information features • R e a d -m o d ify -w rite • T T L -co m p atib le, th re e -s ta te I/O • JEDEC sta n d a rd packages

Contextual Info: S4C256K16E0 5V 256Kx 16 CMOS DRAM EDO Features • Refresh - 5 1 2 refresh cycles, 8 m s refresh interval - RAS-only o r CAS-before-RAS refresh o r self-refresh - Self-refresh o p tio n is available for n e w g en eratio n device • O rganization: 2 6 2 ,1 4 4 w o rd s x 16 bits

6E025

Contextual Info: Features • Refresh • O rganization: 262,144 w o rd s x 16 bits - 512 refresh cycles, 8 ms refresh interval • H ig h speed - 2 5 / 3 0 / 3 5 / 5 0 ns R A S access tim e - RA S-only o r CAS-before-RAS refresh o r self-refresh - 1 2 /1 6 /1 8 /2 5 ns co lu m n address access tim e

Contextual Info: Il High Performance 256Kxl6 CMOS DRAM S4C256K16F0 High Speed 256Kxl6 CMOS DRAM Fast Page Mode PRELIMINARY I F E A TU R E S_ • 512 refresh cycles, 8 ms refresh interval • Organization: 262,144 words by 16 bits - RAS-only or CAS-before-RAS refresh

AS4C256K16E0-60JC

Abstract: as4c256k16eo 12 SQ 045 JF 256KX16 AS4C256K16E0
Contextual Info: H ig h P e r fo r m a n c e 256K X 16 CMOS DRAM gg A S4C 256K 16E 0 II H iah speed 2 5 6 K x l6 CMOS DRAM EDO Preliminary information Features • 5 1 2 r e f r e s h c y c le s, 8 m s r e f r e s h in te rv a l • O r g a n iz a tio n : 2 6 2 , 1 4 4 w o r d s X 16 b its

AS4C256K16F0-60JC

Abstract: sem 2105 16 pin
Contextual Info: Preliminary information Features • R e a d -m o d ify -w r ite • O r g a n iz a tio n : 2 6 2 , 1 4 4 w o r d s b y 16 b its • T T L ~ com p atib le, th r e e -s ta te 1 / O • H ig h s p e e d • JEDEC stan d ard p a ck a g es - 5 0 / 6 0 ns RAS access tim e

L30001

Abstract: D1130
Contextual Info: r H igh Performance 256K X 16 CMOS DRAM gg A S 4C 256K 16E 0 II H igh Speed 2 5 6 K x l6 CMOS DRAM E D O Preliminary Features • 5 1 2 refresh cycles, 8 m s refresh interval • O rganization: 2 6 2 ,1 4 4 w o rd s b y 16 bits • H igh speed - RAS-only o r CAS-before-RAS refresh