8510H
Abstract: i960 Cx Processor Instruction Set Quick Reference 80960CA AP-716 MCON00
Contextual Info: A AP-716 APPLICATION NOTE 80960Cx/80960Jx/80960Hx Architectural Comparison Tom Johnson SPG 80960 Systems Engineer Intel Corporation Mail Stop CH6-311 5000 W. Chandler Blvd. Chandler, Arizona 85226 January 29, 1996 Order Number: 272694-001 Information in this document is provided solely to enable use of Intel products. Intel assumes no liability
|
Original
|
ap-71680960cx/80960jx/80960hxch6-3118510h+3i960 cx processor instruction set quick reference80960camcon00
|
PDF
|
automatic room power control circuit block diagram
Abstract: 80960 80960KB Programmer Reference manual 8-BIT INTELLIGENT CONTROLLER UNIT ICU Three Timer E-NAND tag 8610 stt 7000 NMOS F12 diode I-35 L Diode IR 1254
Contextual Info: i960 Jx Microprocessor User’s Manual September 1994 Order Number: 272483-001 Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which may appear in this document nor does it make a commitment to update the information contained herein.
|
Original
|
index-13index-14automatic room power control circuit block diagram80960+880960kb programmer reference manual8-bit intelligent controller unit icu three timere-nandtag 8610stt 7000nmos f12diode i-35 ldiode ir 1254
|
PDF
|
8424h
Abstract: 8408H 810CH i960HD 8708H
Contextual Info: 1 Programming Environment This chapter describes the i960 Jx processor’s programming environment including global and local registers, control registers, literals, processor-state registers and address space. 1.1 Overview The i960 architecture defines a programming environment for program execution, data storage and
|
Original
|
80960jx8424h8408h810ch+2i960hd8708h
|
PDF
|
intel atom microprocessor
Abstract: PC 80960 001-page 272495 32-bit intel microprocessor architecture dcct i960 Cx Instruction Set Quick Reference S-809 8448H 80960HD
Contextual Info: 80960HA/HD/HT SPECIFICATION UPDATE Release Date: July, 1996 Order Number 272830-001 The 80960HA/HD/HT may contain design defects or errors known as errata. Characterized errata that may cause the 80960HA/HD/HT’s behavior to deviate from published specifications
|
Original
|
80960ha/hd/htintel atom microprocessorpc 80960001-page+727249532-bit intel microprocessor architecturedccti960 cx instruction set quick references-8098448h80960hd
|
PDF
|
HTR resistors
Abstract: 80960 80960SA reference i960 RP Processor 80960JF STT 433 1250H clock generator in dual core processor i960 Cx Instruction Set Quick Reference i960 Cx Processor Instruction Set Quick Reference
Contextual Info: i960 RP Microprocessor User’s Manual i960® RP Microprocessor User’s Manual February 1996 Order Number: 272736-001 Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for
|
Original
|
index-17index-18htr resistors80960+880960sa referencei960 rp processor80960jfstt 4331250hclock generator in dual core processori960 cx instruction set quick referencei960 cx processor instruction set quick reference
|
PDF
|
80960
Abstract: BO 620 bbc timer stt 11 c17f i960 Cx Processor Instruction Set Quick Reference i960RP 80960JF 80960RD 80960RP MA11
Contextual Info: i960 Rx I/O Microprocessor Developer’s Manual Release Date: April, 1997 Order Number: 272736-002 The i960® Rx I/O Processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Such errata are
|
Original
|
sa-26index-2380960bo 620+8bbc timer stt 11c17fi960 cx processor instruction set quick referencei960rp80960jf80960rd80960rpma11
|
PDF
|
BG 616
Abstract: processor cross reference D-10 D-12 D-16 D-18 D-19 5252 F 1118 intel i960 RISC nsp 1337
Contextual Info: i960 Jx Microprocessor Developer’s Manual Release Date: December, 1997 Order Number: 272483-002 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of
|
Original
|
index-17bg 616processor cross referenced-10+7d-12d-16d-18d-195252 f 1118intel i960 riscnsp 1337
|
PDF
|
80960Rm
Abstract: aaaz 80960RN 0x00001450 0x00001204 0x0000101B 0x00001240
Contextual Info: 80960RM/RN Processor Initialization: Programming Guide & Initialization Code Application Note August 1998 Order Number: 273166-001 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
|
Original
|
80960rm/rnic960asm960lnk960+8cof96080960rmaaaz80960rn0x000014500x000012040x0000101b0x00001240
|
PDF
|
0x00001538
Abstract: 0x00001019 0x00001804 0x00001017 0x00001240 0x00001050 IOP303 1000H 80303 0x0000140c
Contextual Info: Intel 80303 I/O Processor Initialization: Programming Guide and Initialization Application Note April 2001 Order Number: 273395-005 Intel® 80303 I/O Processor Initialization: Programming Guide and Initialization Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
|
Original
|
gcc960gas960eev303ibrev303+100x000015380x000010190x000018040x000010170x000012400x00001050iop3031000h803030x0000140c
|
PDF
|
LB 124 d
Abstract: BH RV transistor i960 Cx Processor Instruction Set Quick Reference 80960JT 80960RM 80960RN REQ64 BIT3102 273160 80960
Contextual Info: i960 RM/RN I/O Processor Developer’s Manual July 1998 Order Number: 273158-001 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability
|
Original
|
80960rxjxindex-11lb 124 dbh rv transistor+8i960 cx processor instruction set quick reference80960jt80960rm80960rnreq64bit310227316080960
|
PDF
|
GC80960RS100
Abstract: p16c182 P16C180V GC80960RN100 I960R 1250H capacitor 106c intel schematics 80960RM 80960RN
Contextual Info: Intel i960® RM/RN/RS I/O Processor Specification Update September 4, 2001 Notice: The 80960RM/RN/RS processor may contain design defects or errors known as errata. Characterized errata that may cause the product’s behavior to deviate from pubished specifications are documented in this specification update.
|
Original
|
80960rm/rn/rsgc80960rs100p16c182p16c180v+7gc80960rn100i960r1250hcapacitor 106cintel schematics80960rm80960rn
|
PDF
|
272495
Abstract: FF30 272484 80960HX 80960HA
Contextual Info: Converting Designs from the 80960HA/HD/HT Embedded Processors to the 80960JA/JF/JD/JT White Paper May 1998 Order Number: 273171-001 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
|
Original
|
80960ha/hd/ht80960ja/jf/jd/jt80960jtlcd-960+780960hx80960jxcom/design/i960/swsup/272495ff3027248480960ha
|
PDF
|
intel 8096 instruction set
Abstract: A23 1101 01A intel 8096 assembly language schematic diagram intel atom intel 8098 non interruptible and burst and memory tag 8634 CT3 current sensing instructio set of 8088 microprocessor I960 hx
Contextual Info: i960 Hx Microprocessor User’s Manual i960® Hx Microprocessor User’s Manual November 1995 Order Number: 272484-001 Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of
|
Original
|
intel 8096 instruction seta23 1101 01aintel 8096 assembly languageschematic diagram intel atom+6intel 8098non interruptible and burst and memorytag 8634ct3 current sensinginstructio set of 8088 microprocessori960 hx
|
PDF
|
PC 80960
Abstract: processor chart 80960RM 80960RN FF34H ROUND ROBIN ARBITRATION AND FIXED PRIORITY A6410
Contextual Info: Initialization and System Requirements 11 This chapter describes the steps that the i960 RM/RN I/O processor performs during initialization. Discussed are the reset modes, the reset state and built-in self test BIST features. This chapter also describes the processor’s basic system requirements — including power, ground
|
Original
|
pc 80960processor chart80960rm80960rn+3ff34hround robin arbitration and fixed prioritya6410
|
PDF
|
|
|
272484-001
Abstract: 272495 TTL catalog 8448H 272484 i960HA FAH 19 hx 630 A8A17 Intel i960 Hx
Contextual Info: i960 Hx Microprocessor User’s Manual i960® Hx Microprocessor User’s Manual November 1995 Order Number: 272484-001 Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of
|
Original
|
272484-001272495ttl catalog8448h+6272484i960hafah 19hx 630a8a17intel i960 hx
|
PDF
|
80960JA
Abstract: 80960JD 80960JF 272852 intel DOC 80960 272483
Contextual Info: i960 Jx PROCESSOR SPECIFICATION UPDATE Release Date: April, 1997 Order Number: 272852-002 The i960® Jx Processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Such errata are not
|
Original
|
80960jx12345678h80960ja80960jd+480960jf272852intel doc80960 272483
|
PDF
|
272484
Abstract: A2Y 4h 80960MX
Contextual Info: in t J AP-716 APPLICATION NOTE 80960Cx/80960Jx/80960Hx Architectural Comparison January 29, 1996 Order Number: 272694-001 1-607 in y 1.0 AP-716 Introduction This document describes three implementations of the i960 architecture: the 80960Cx, 80960Jx, and 80960Hx
|
OCR Scan
|
ap-71680960cx/80960jx/80960hx80960cx80960jx+580960hx8096y272484a2y 4h80960mx
|
PDF
|
Date Code Formats intel
Abstract: 141 mrc Intel 80200 272484 0004H 0040H CP14 CP15 80960HX INTEL Date Code Formats
Contextual Info: Intel i960® Processor and Intel® XScale Processor Initialization Comparison Technical Note February 2001 Order Number: 273486-001 Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual
|
Original
|
date code formats intel141 mrcintel 80200272484+60004h0040hcp14cp1580960hxintel date code formats
|
PDF
|
intel 8255
Abstract: 8255 intel microprocessor block diagram gigabyte MOTHERBOARD CIRCUIT diagram dac 8419 block diagram of intel 8255 chip GC80960RP3V33 gigabyte motherboard BUS BAR specification fast page mode dram controller microprocessor 8255 application
Contextual Info: i960 RP/RD I/O PROCESSOR SPECIFICATION UPDATE Release Date: March, 1999 Order Number: 272918-020 The i960® RP/RD I/O Processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are documented in this Specification Update.
|
Original
|
80960rp/rd80960rp80960rdintel 8255+98255 intel microprocessor block diagramgigabyte motherboard circuit diagramdac 8419block diagram of intel 8255 chipgc80960rp3v33gigabyte motherboardbus bar specificationfast page mode dram controllermicroprocessor 8255 application
|
PDF
|
CAPACITOR VALUE TABLE
Abstract: FF39
Contextual Info: Initialization and System Requirements 1 This chapter describes the steps that the i960 Jx processor performs during initialization. Discussed are the RESET# pin, the reset state, and built-in self test BIST features. This chapter also describes the processor’s basic system requirements — including power, ground and clock —
|
Original
|
80960jxcapacitor value tableff39 |
PDF
|
8424h
Abstract: 1488h 1250H 103DH 1428H 1484H 1118H 8620H 1278H 8420H
Contextual Info: Memory-Mapped Registers C This chapter describes the memory-mapped registers for the integrated peripherals. C.1 Overview The Peripheral Memory-Mapped Register PMMR interface gives software the ability to read and modify internal control registers. Each register is accessed as a memory-mapped 32-bit register
|
Original
|
32-bit1838h1828h183ch+1518ffh1810h180ch1710h80960rm/rn8424h1488h1250h103dh1428h1484h1118h8620h1278h8420h
|
PDF
|
80960RD
Abstract: 80960RP GC80960RD66 GC80960RP33 GC80960RP3V33 272918 intel DOC 80960RD66
Contextual Info: i960 RP/RD I/O PROCESSOR SPECIFICATION UPDATE Release Date: April, 1998 Order Number: 272918-017 The i960® RP/RD I/O Processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are documented in this Specification Update.
|
Original
|
80960rd80960rpgc80960rd66gc80960rp33+4gc80960rp3v33272918intel doc80960rd66
|
PDF
|
80960RD
Abstract: 80960RP GC80960RD66 GC80960RP33 GC80960RP3V33 272918 BIT3102
Contextual Info: i960 RP/RD I/O PROCESSOR SPECIFICATION UPDATE Release Date: May, 1998 Order Number: 272918-018 The i960® RP/RD I/O Processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are documented in this Specification Update.
|
Original
|
80960rd80960rpgc80960rd66gc80960rp33+3gc80960rp3v33272918bit3102
|
PDF
|
bbc timer stt 11
Contextual Info: Index A absolute displacement addressing mode 2-5 memory addressing mode 2-5 offset addressing mode 2-5 AC 3-14 AC register, see Arithmetic Controls AC register access faults 3-7 access types restrictions 3-6 ADD 6-6 add conditional instructions 6-6 integer instruction 6-10
|
Original
|
80960rxjxindex-11bbc timer stt 11 |
PDF
|