PL27 Search Results

SuperSpeed USB 3.0 to Serial ATA Bridge

Abstract: PL2771 USB3.0 PL-2771 generic SPI USB3.0 phy
Contextual Info: PL-2771 Product Brochure v1.2 5/28/10’ PL2771 SuperSpeed USB3.0 to SATAII Bridge Controller OVERVIEW The PL2771 is a single-chip SuperSpeed USB3.0 to SATAII compliant bridge controller that is designed to perform seamless protocol transfer between the USB3.0 and SATAII interface. It supports latest USB3.0

Contextual Info: Zener Diodes 1W Type No. Device Marking Code PL3V6C PL3V9C PL4V3C PL4V7C PL5V1C PL5V6C PL6V2C PL6V8C PL7V5C PL8V2C PL9V1C PL10C PL11C PL12C PL13C PL15C PL16C PL18C PL20C PL22C PL24C PL27C PL30C PL33C PL36C PL39C PL43C PL47C PL51C PL56C PL62C PL68C PL75C PL82C

PL-2773

Abstract: esata usb diagram PL2773 sata phy SuperSpeed USB 3.0 to Serial ATA Bridge spi sata controller usb sata controller sata TO ESATA USB3.0 PL-277
Contextual Info: PL-2773 Product Brochure v1.0 8/01/10’ PL2773 USB3.0/eSATAII to SATAII Bridge Controller OVERVIEW The PL2773 is a single-chip SuperSpeed USB3.0 or eSATAII to SATAII compliant bridge controller that is designed to perform seamless protocol transfer between the USB3.0/eSATA and SATAII interface. The

L25C

Abstract: l24c PL30D ORLI10G BM680
Contextual Info: ORLI10G Data Sheet Revision History Date Version Page November, 2003 January, 2004 6 6.1 78 April, 2004 7 57-58 Change Summary Previous Release Added lead-free package designator. Updated Table 16. PBGA Pinout Table; Pin Description BM680 Pin Pair PL27B L23C_D0

PL2771

Abstract: sata phy crystal oscillator DOC-70 generic SPI qfn48 LQFP64 0x2771 PL-277 LQFP64 package usb to sata circuit diagram
Contextual Info: PL2771 SuperSpeed USB 3.0 SATA Bridge Controller Product Datasheet Premilinary Document Revision: 0.9E Document Release: February 3, 2010 Prolific Technology Inc. 7F, No. 48, Sec. 3, Nan Kang Rd. Nan Kang, Taipei 115, Taiwan, R.O.C. Tel: 886-2-2654-6363

00XXX001

Abstract: BA 5979 R15C3 OR3T125 OR3T20 OR3T30 OR3T55 PT10 PT11 PT12
Contextual Info: Data Sheet November 2006 ORCA Series 3C and 3T Field-Programmable Gate Arrays Features • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Baseline FPGA family used in Series 3+ FPSCs field programmable system chips which combine FPGA logic

AH202-2

Abstract: SYPS-2-252
Contextual Info: Surface Mount Power Splitter/Combiner 2 Way-0° 50Ω 5 to 2500 MHz Maximum Ratings Features Operating Temperature Storage Temperature SYPS-2-252+ • wideband, 5 to 2500 MHz. useable 0.5 to 2800 MHz • low amplitude unbalance, 0.1 dB typ. • low phase unbalance, 1 deg. typ.

transistor pt36c

Abstract: gp714 diode GP113 transistor pt42c diode gp116 GP114 GP021 PT36c gp627 GP111
Contextual Info: OR4E FPGA Ver 2.0 1 4/1/2002 Lattice Semiconductor Corp Series 4 FPGA Evaluation Board Diagram Revision 2.0 OR4E FPGA Ver 2.0 2 4/1/2002 Lattice Semiconductor Corp JTAG Programming Connection J55 Schematic page 4 An 8-pin connection to the JTAG interface used for programming.

TPE11

Abstract: TPT20 CON6A v2 tpr4 pr48b PT13B condor E5 Condor LVCMOS15 LVCMOS25
Contextual Info: LatticeEC Standard Evaluation Board – Revision B User’s Guide April 2007 ebug10_01.4 Lattice Semiconductor LatticeEC Standard Evaluation Board – Revision B User’s Guide Introduction The LatticeEC Standard Evaluation Board provides a convenient platform to evaluate, test and debug user

OSC4/SM

Abstract: MDLS-20265 OPTREX C-51505 MDLS-24265 short stop 12v p18 30a rs232 converter dmx Mosfet J49 LCM-S01602 lcm-s02402 Vishay SOT23 MARKING F5
Contextual Info: LatticeXP2 Advanced Evaluation Board User’s Guide January 2009 Revision: EB30_01.3 LatticeXP2 Advanced Evaluation Board User’s Guide Lattice Semiconductor Introduction The LatticeXP2 Advanced Evaluation Board provides a convenient platform to evaluate, test and debug user

CON6A

Abstract: K4T51163QG-HCE60 pDS4102-DL2 LVCMOS33 LVCMOS15 LVCMOS25 PB50B TPE11 PL43A FPGA48
Contextual Info: LatticeEC Standard Evaluation Board – Revision A User’s Guide April 2007 EB07_02.4 Lattice Semiconductor LatticeEC Standard Evaluation Board – Revision A User’s Guide Introduction The LatticeEC Standard Evaluation Board provides a convenient platform to evaluate, test and debug user

LC4064ZE

Abstract: BSDL Files infineon LFXP6C-3FN256I "x-ray machine" K4H560838E LC4064 LC4256ZE LFXP10C-3F256I LFxP3C-3TN144C PCI x1 express PCB dimensions artwork
Contextual Info: LatticeXP Family Handbook HB1001 Version 03.4, September 2010 LatticeXP Family Handbook Table of Contents September 2010 Section I. LatticeXP Family Data Sheet Introduction Features . 1-1

30021

Abstract: L48C L41C IC L44C DATASHEET L30C l31c L43C ORSO42G5 ORSO82G5 ORT42G5
Contextual Info: ORCA ORSO42G5 and ORSO82G5 0.6 - 2.7 Gbps SONET Backplane Interface FPSCs August 2005 Data Sheet Introduction Lattice has extended its family of high-speed serial backplane devices with the ORSO42G5 and ORSO82G5 devices. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the ORSO42G5 and

CB4CLE

Abstract: cb4re CB8CLED cb8cle CB4CLED X74-160 x4202 CB16CE sr4cled 2 bit magnitude comparator using 2 xor gates
Contextual Info: ON LIN E R LIBRARIES G UI DE T ABL E OF CONT ENT S INDEX GO T O OT HER BOOKS 0 4 0 1410 Copyright 1993-1995 Xilinx Inc. All Rights Reserved. Contents Chapter 1 Xilinx Unified Libraries Overview .

MRC D6 16A

Contextual Info: Cover Marvell PXA270 Processor Developers Manual Doc. No. MV-S301039-00 , Rev. A April 2009 Marvell. Moving Forward Faster Released PXA270 Processor Developers Manual Document Conventions Note: Provides related information or information of special importance.

syscon

Abstract: LFEC1E-3T100C ips works 6CW3
Contextual Info: LatticeECP/EC Family Data Sheet Version 01.3 LatticeECP/EC Family Data Sheet Introduction November 2004 Preliminary Data Sheet Features − − − − − − • Extensive Density and Package Options • 1.5K to 41K LUT4s • 65 to 576 I/Os • Density migration supported

RAS 0510 SUN HOLD

Abstract: relay ras 1210 sun hold RAS 0510 relay RAS 0510 RAS 0510 SUN HOLD ras 0910 sun hold RAS 0610 ERF 2030 ras 0610 relay 45n03
Contextual Info: Compiled by Herman Boel & James Niven EMWG homepage: www.emwg.info 1998-2005 Preface & Copyright Welcome to the Euro-African Medium Wave Guide What lies in front of you or what you see on your computer screen is the result of a lot of hard work and love.

SBC-GX1

Abstract: nec nl6448ac33-18 lcd service manual Floppy connector 34 pin IDC to usb Module42 SDCFB Arcom pentium NL6448AC33-18 LCD NEC NL6448BC20-08 PL11 aim104
Contextual Info: SBC-GX1 Windows XP Embedded Quickstart SBC-GX1 Windows XP Embedded Development Kit Quickstart Manual www.arcom.com a company SBC-GX1 Windows XP Embedded Quickstart Definitions Arcom is the trading name for Arcom Control Systems Inc and Arcom Control Systems Ltd.

Contextual Info: Surface Mount Directional Coupler 50Ω D20C+ 810 to 960 MHz Maximum Ratings Operating Temperature Features Storage Temperature -65°C to 150°C Permanent damage may occur if any of these limits are exceeded. Pin Connections INPUT 4 OUTPUT 6 COUPLED 3 GROUND

d19g

Contextual Info: Surface Mount D19G+ D19G Directional Coupler 50Ω 1420 to 1660 MHz Maximum Ratings Operating Temperature Features Storage Temperature -65°C to 150°C Permanent damage may occur if any of these limits are exceeded. Pin Connections INPUT 4 OUTPUT Reel Size

Contextual Info: LatticeXP Family Data Sheet Version 04.4, April 2006 LatticeXP Family Data Sheet Introduction December 2005 Data Sheet • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2 − LVTTL

Contextual Info: LatticeXP Family Data Sheet Version 03.0, September 2005 LatticeXP Family Data Sheet Introduction July 2005 Advance Data Sheet • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2

Contextual Info: ORCA ORLI10G Quad 2.5Gbps, 10Gbps Quad 3.125Gbps, 12.5Gbps Line Interface FPSC August 2004 Data Sheet Introduction The Lattice ORCA Series 4-based ORLI10G FPSC combines a high-speed line interface with a flexible FPGA logic core. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the ORLI10G consists

pt45

Contextual Info: LatticeSC Family Data Sheet DS1004 Version 01.2, June 2006 LatticeSC Family Data Sheet Introduction June 2006 Preliminary Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 132 to 942 I/Os • 700MHz global clock; 1GHz edge clocks