SYSCON Search Results

MD500

Abstract: automatic daisy chain VME VME DAISY CHAIN 700C1
Contextual Info: NEWBRIDGE MICROSYSTEMS CRUMBS' 2SE D • tSôfllOl 0 0 0 0 b 7 ô 3 CAS1C014 VMEbusAVICS CONTROL CIRCUIT ÀCC T-52 -33 -55 • Full VMEbus system controller functions • Auto-ID slot Identification • Automatic VMEbus SYSCON Identification • The CA91C014 Advanced System Architecture Control

HV-DK510MKII

Abstract: 88525-205M HV-DK910MKH MN67481
Contextual Info: Przegl^d rozwi^zan ukladowych MECHACON i SYSCON Ze wzgl^du na ograniczony rozmiar strony ksicjzki oraz znaczn^ ilosci^ r ìó zek" procesorów pokazemy tylko uklad ich wyprowadzen o symboliczrue za/naczonej komunikacji z innymi blokami funkcjonalnymi, czujnikami i uklad cimi

STK 7226

Abstract: STK7226 STK 7226 sanyo Sanyo STK STK SANYO stk ic Sanyo STK 7360 7226 zasilacz STK7360
Contextual Info: 158 Przegl^d rozwi^zan ukiadowych MECHACON 1 SYSCON Rys. 74. Struktur a w ew n çtrzn a ukladu STK /226 Scalony uklad hybrydowy STK 7226 umozliwia zbudowanie przetwornic/ napiçcia zasilanej napiçciem stalym rzçdu 40 V wyprowadzenia 6 do 15 or iz klasycznego stabilizatora (wyprowadzenia 1 do 5). Poniewaz jest to rozwiazanie niezbyt uniwersalne (szczegölnie gdy zechcem y dobrac wlasciwy

Carlo Gavazzi syscon

Abstract: SW023 Carlo dupline 128 EMU 9091 syscon D7191SW023 7191 g34910090
Contextual Info: Du line Accessories Software Fieldbus Installationbus SYSCON Terminal Emulator Software Type D 9091 Product Description allow menu driven configuration of the master generator D 3890 . and the modem interface D 9091 . . The SYSCON terminal emulator software is used to convert standard IBM compatible

W25PXX

Abstract: M25PXX AT25Fxx IEEE1532 JTAG1532 LVCMOS33 TN1053 0.22j S25FLxx
Contextual Info: TN1053_02.2J Apr. 2006 LatticeECP/EC sysCONFIG 使用ガイド はじめに LatticeECPとLatticeEC FPGA内にあるメモリは揮発性のSRAMが用いられています。電源がなくなると、 SRAMセルはそれらに蓄えている情報を失います。そのためパワーアップ時と更新する必要がある時はいつ

TN1169

Abstract: ECP3-35 ECP3-95 LVCMOS33 64SED lattice ECP3 slave SPI Port
Contextual Info: LatticeECP3 sysCONFIG Usage Guide June 2010 Technical Note TN1169 Introduction Configuration is the process of loading or programming a design into volatile memory of an SRAM-based FPGA. This is accomplished via a bitstream file, representing the logical states, that is loaded into the FPGA internal configuration SRAM memory. The functional operation of the device after programming is determined by these internal

MX25Lxx

Abstract: M25PXX LVCMOS33 ISPVM embedded
Contextual Info: LatticeECP2/M sysCONFIG Usage Guide June 2010 Technical Note TN1108 Introduction The configuration memory in the LatticeECP2 and LatticeECP2M™ FPGAs is built using volatile SRAM; therefore, an external non-volatile configuration memory is required to maintain the configuration data when the power is

Contextual Info: C R L H B W CA91C014 ' VMEbusAVICS CONTROL CIRCUIT ACC • Full VMEbus system controller functions • Auto-ID slot Identification • Automatic VMEbus SYSCON identification • Bus Isolation (Bl-mode ) controller • Multiple VMEbus request and release options

DI-124

Abstract: JTAG1149 JTAG1532 LFXP10 LVCMOS33 JTAG-1149
Contextual Info: TN1082_01.5J Aug. 2007 LatticeXP sysCONFIG 使用ガイド はじめに パワーアップ時やユーザがデバイスを更新したい時はいつでもコンフィグレーション・メモリに自動的に ロードすることができるように、SRAMセルに伴って、LatticeXP TM FPGAにおいてはフラッシュ・セルを

mx25lx

Abstract: M25PXX w25pxx LVCMOS33 ECP26 Nexflash MX25Lxx
Contextual Info: LatticeECP2/M sysCONFIG Usage Guide September 2008 Technical Note TN1108 Introduction The configuration memory in the LatticeECP2 and LatticeECP2M™ FPGAs is built using volatile SRAM; therefore, an external non-volatile configuration memory is required to maintain the configuration data when the power is

upc3393

Abstract: NJM2352 syscon an3794 jm23
Contextual Info: 160 U Przegl^d rozwi4zan ukladowvch MECHACON i SYSCON k l a d y p o m o c n ic z e W wi^kszosci uklady pomocnicze w obwodach procesora system co ntr.' •to: ♦ uklady steruj^ce silnikami komutatorowymi, ♦ specjalizowane wzmacniacze operacvjne. Umieszczone

LFSC25

Abstract: TN1100 slash memory
Contextual Info: LatticeSC sysCONFIG Usage Guide October 2008 Technical Note TN1080 Introduction Configuration is the process of loading or programming a design into volatile memory of an SRAM-based FPGA. This is accomplished via a bitstream file, representing the logical states, that is loaded into the FPGA internal configuration SRAM memory. The device’s functional operation after being programmed is determined by these internal configuration RAM settings. The SRAM cells must be loaded with configuration data each time the device

Contextual Info: OEC 0 3 19 Œ U E U S ' MLV,m CA91C014 VMEbusAVICS CONTROL CIRCUIT ACC) • Full VMEbus system controller functions • Auto-ID slot Identification • Automatic VMEbus SYSCON Identification • Bus isolation (Bi-mode®) controller • Multiple VMEbus request and release options

STK5342

Abstract: STK5464 stk 5342 U212
Contextual Info: 154 Przeg^d rozwi^zañ ukiadowych MHCHACON i SYSCON Rys . 66, Strukt u ra w c w n ç tr z na ukiadu STK 5363 Do podstawowych parametrów ukladu STK 53632 nalez^: ♦ Maksymalne napiçcia zasilania U = 30 V ♦ Napiçcie wyjsciowe U2= 12 V przy maksymalnym pr^dzie 1 A,

c32w

Contextual Info: NEWBRIDGE C R u MICROSYSTEMS m m S5E D • LSfifllQl Q O O O b ? a 3 ' c a s ic o 1 4 VMEbusAVICS CONTROL CIRCUIT ACC T -5 2 -3 3 -5 5 • Full VMEbus system controller functions • Auto-ID slot Identification • Automatic VMEbus SYSCON Identification

STK5473

Abstract: stk 5473 stk 5477 STK5477 5473
Contextual Info: 156 Przegl^d rnzwiazan ukìadowvch MECHACON i SYSCON Rys. 70. Struk tu ra w e w n ç trzna u klad u STK 5473 Do podstaw ow ych param etrów ukladu STK 5473 nalez^: ♦ Maksymalne napiçcia zasilania U = 30 V ♦ Napiçcie wyjsciowe U2 = 5,8 V przy maksymalnym pr^dzie 1,3 A,

TN1137

Abstract: lattice xp2 slave spi port LVCMOS33 XP2-17 TN1141
Contextual Info: LatticeXP2 sysCONFIG Usage Guide June 2009 Technical Note TN1141 Introduction The memory in the LatticeXP2 FPGAs is built using Flash cells, along with SRAM cells, so that configuration memory can be loaded automatically at power-up, or at any time the user wishes to update the device. In addition

M25PXX

Abstract: spi flash m25pxx LVCMOS33
Contextual Info: LatticeECP/EC sysCONFIG Usage Guide September 2008 Technical Note TN1053 Introduction The memory in LatticeECP and LatticeEC™ FPGAs is built using volatile SRAM. When the power is removed, the SRAM cells lose their contents. A supporting non-volatile memory is required to configure the device on powerup and at any time the device needs to be updated. The LatticeECP/EC devices support a sysCONFIG™ interface

KDS 1.540

Abstract: bq30ut
Contextual Info: OEC t 3 199' TM C R JULY 1991 CA91C014 L VMEbus AVICS CONTROL CIRCUIT ACC) Full VMEbus system controller functions Auto-ID slot Identification Automatic VMEbus SYSCON Identification Bus Isolation (Bl-mode*) controller Multiple VMEbus request and release options

MX25Lxx

Abstract: M25PXX ISPVM embedded TN1108 W25PXX IEEE1532 LVCMOS33 M100 AT25Fxx p1519
Contextual Info: TN1108_02.1J Sept. 2008 LatticeECP2/M sysCONFIG 使用ガイド はじめに LatticeECP2 とLatticeECP2M™ FPGA内にあるコンフィグレーション・メモリは揮発性のSRAMが用い られています。電源がなくなると喪失するコンフィグレーション・データを保持する不揮発メモリが必要で

ECP3-35

Abstract: ECP3-95 LVCMOS33 TN1169 lattice ECP3 slave SPI Port 64SED crc 64 GOE11
Contextual Info: LatticeECP3 sysCONFIG Usage Guide January 2010 Technical Note TN1169 Introduction Configuration is the process of loading or programming a design into volatile memory of an SRAM-based FPGA. This is accomplished via a bitstream file, representing the logical states, that is loaded into the FPGA internal configuration SRAM memory. The device’s functional operation after being programmed is determined by these internal configuration RAM settings. The SRAM cells must be loaded with configuration data each time the device

6206a

Abstract: K-Line transceiver w1p 84 st10f2xx sigma asc 333 24 pin K-line ST10F276E W1P 59 st10 Bootstrap st10273e
Contextual Info: ST10F276E 16-bit MCU with MAC unit 832 Kbyte Flash memory and 68 Kbyte RAM Datasheet − production data Features • ■ ■ ■ ■ ■ Highly performance 16-bit CPU with DSP functions – 31.25ns instruction cycle time at 64MHz max CPU clock – Multiply/accumulate unit MAC 16 x 16-bit

intel date code marking NAND Flash

Abstract: ARMv5TE instruction set MLC nand 2012 153 ball eMMC memory flash controller usb state machine for ahb to apb bridge iNAND eMMC 4 41 emmc spi bridge emmc bga 162 LPC3130FET180
Contextual Info: LPC3130/3131 Low-cost, low-power ARM926EJ-S MCUs with high-speed USB 2.0 OTG, SD/MMC, and NAND flash controller Rev. 2 — 29 May 2012 Product data sheet 1. General description The NXP LPC3130/3131 combine an 180 MHz ARM926EJ-S CPU core, high-speed USB 2.0 On-The-Go OTG , up to 192 KB SRAM, NAND flash controller, flexible external bus

18n5o

Abstract: BA2N15 SGX530 PowerVR SGX530 0x4803 Ps3 MOTHERBOARD CIRCUIT diagram DDR2-800 AM38x 15F4 17 inch lcd monitor
Contextual Info: AM3894 AM3892 www.ti.com SPRS681A – OCTOBER 2010 – REVISED MARCH 2011 AM389x Sitara ARM Microprocessors MPUs Check for Samples: AM3894, AM3892 1 Device Summary 1.1 Features • High-Performance Sitara ARM Microprocessors (MPUs) – ARM® Cortex™-A8 RISC MPU