U212 Search Results

A1619A

Abstract: b1241
Contextual Info: SN54ABT32318, SN74ABT32318 18-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS SCBS180A-JUNE 1 9 9 2 - REVISED JULY 1994 Members of the Texas Instruments Wldebus+ Family State-of-the-Art EPIC-IlB™ BICMOS Design Significantly Reduces Power Dissipation Typical V q l p Output Ground Bounce

Contextual Info: TIBPAL22V10-20M HIGH-PERFORMANCE IMPACT-X PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPSQ12A - D3523, JUNE 1 9 9 0 -R E V IS E D MARCH 1992 JT P A C K A G E Second-Generation PLD Architecture TO P V IE W High-Performance Operation: fmax (External Feedback). . . 33.3 MHz

Contextual Info: SN75LBC241 LOW-POWER LinBiCMOS MULTIPLE DRIVERS AND RECEIVERS SLLS137E - MAY 1992 - REVISED JANUARY 1999 • Operates With Single 5-V Power Supply • Meets or Exceeds the Requirements of TIA/EIA-232-F and ITU Recommendation V.28 • Improved Performance Replacement for

tlc3741

Abstract: resistor network 104g 9 pin
Contextual Info: TLC374, TLC374Q, TLC374Y LinCMOS QUADRUPLE DIFFERENTIAL COMPARATORS SLCS118A-NOVEMBER 1983-R EVISED OCTOBER 1996 • Single- or Dual-Supply Operation D, J, N, OR PW PACKAGE TOP VIEW • Wide Range of Supply Voltages 2 V to 18 V u 10UT[ • Very Low Supply Current Drain 0.3 mA Typ

Contextual Info: TLC339M, TLC339I, TLC339C QUADRUPLE MICROPOWER LinCMOS COMPARATORS D3135, DECEMBER 1986-R EV ISED FEBRUARY 1989 • Very Low Power. . . 200 jjiW Typ at 5 V T LC 339M . . . J PACKAGE TLC339I. TLC339C . . . D. J, OR N PACKAGE • Fast Response Time . . . 2.5 |xs Typ with

LVC244

Contextual Info: I SN74LVC241 OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS SGAS343 - MARCH 1994 DB, DW, OR PW PACKAGE TOP VIEW E P IC (Enhanced-Performance Implanted CMOS) Submicron Process Typical V q lp (Output Ground Bounce) < 0.8 V at Vc c = 3.3 V, TA = 25°C Typical V q HV (Output V qh Undershoot)

1d4 cb

Contextual Info: SN54ABT16373A, SN74ABT16373A 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS S CB S160 - DE CE M B E R 1992 Members of the Texas Instruments Widebus Family SN54ABT16373A . . . WD PACKAGE SN74ABT16373A . . . DGG OR DL PACKAGE TOP VIEW State-of-the-Art EPIC-llB™ BiCMOS Design

Contextual Info: SN74LVC540 OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS JA N U A R Y 1993 • Space-Saving Package Option: Shrink Small-Outline Package DB Features EIAJ 0.65-mm Lead Pitch DB, DW, OR PW PACKAGE (TOP VIEW) • EPIC (Enhanced-Performance implanted CMOS) Submicron Process

UC494

Contextual Info: SSSSSÄ UNITRODE UC494A UC495A UC494AC UC495AC Advanced Regulating Pulse Width Modulators FEATURES • Dual u n com m itted 40V, 2 0 0 m A output tran sistors » 1% a ccu rate 5V reference • Dual error am p lifie rs • W ide range, v a riab le dead tim e

PAL16L8 programming specifications

Abstract: TIBPAL16R4 TIBPAL16L8
Contextual Info: TIBPAL16L8-20M. TIBPAL16R4 20M, TIBPAL16R6 20M, TIBPAL16R8 20M TIBPAL 16L8-15C, TIBPAL16R4 15C, TIBPAL 16R615C, TIBPAL 16R8 15C HIGH-PERFORMANCE IMPACT PAL CIRCUITS FEBRUARY 1984-REVISED DECEMBER 1987 • High-Performance Operation Propagation Delay M Suffix . . . 20 ns Max

Contextual Info: SN74LVC137 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER WITH ADDRESS LATCHES SCAS340 - MARCH 1994 » EPIC Enhanced-Performance Implanted CMOS Submicron Process • Typical V o lp (Output Ground Bounce) D, DB, OR PW PACKAGE (TOP VIEW) A[ B[ c[ Ü2A [ S2B[ G1[

CO2V

Contextual Info: SN74ALVC16600 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS JA N U A R Y 1993 Member of the Texas Instruments Widebus Family DGG OR DL PACKAGE TOP VIEW ÖEÄE [ LEAB [ A1 [ GND [ A2 [ A3 [ EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process

Contextual Info: SN74LVC16543 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS 3CAS317A- NOVEMBER 1993 - REVISED OCTOBER 199S | • Member of the Texas Instruments Wldobua Family • EP/C™ Enhanced-Performance Implanted CMOS Submicron Process • Typical V q l p (Output Ground Bounce)

51A-2

Contextual Info: SN54ABT16470, SN74ABT16470 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS S CBS085B - D3794, FEBR UARY 1991 - R EVISED JULY 1993 SN54ABT16470. . WD P ACKAG E SN74ABT16470. . DL P ACKAG E TOP VIEW Members of the Texas Instruments Widebus Family State-of-the-Art EPIC-UB ™ BiCMOS Design

Contextual Info: SN74LVC841 10-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS M ARCH 1993 OB, DW, OR PW PACKAGE TOP VIEW • Space-Saving Package Option: Shrink Small-Outline Package (DB) Features EIAJ 0.65-mm Lead Pitch • EPIC (Enhanced-Performance Implanted

Contextual Info: I SN74LVC158 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTOR/MULTIPLEXER SCAS342 - MARCH 1994 D, DB, OR PW PACKAGE TOP VIEW EPIC (Enhanced-Performance Implanted CMOS) Submicron Process Typical V q l p (Output Ground Bounce) < 0.8 V at Vc c = 3.3 V, TA = 25°C

2N6797

Contextual Info: POWER MOSFET TRANSISTORS JTX JTXV 200 Volt, 0.4 Ohm N-Channel DESCRIPTION The U nitrode power M O SFET design u tilizes the m ost advanced technology available. This efficien t design ach ieves a very low Rosiom and a high transconductance. FEATURES • Fast Sw itching

SN54LV14

Abstract: 2020CN
Contextual Info: SN54LV14, SN74LV14 HEX SCHMITT-TRIGGER INVERTERS _ S C L S 1 8 7 B - FEBRUARY 1 9 9 3 - REVISED APRIL 1996 EPIC Enhanced-Performance Implanted CMOS 2-|i Process SN54LV14 . . . J OR W PACKAGE SN74LV14. . . D, DB, OR PW PACKAGE (TOP VIEW) TVplcal V q l p (Output Ground Bounce)

Contextual Info: SN74LVC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET JANUARY 1993 D, DB, OR PW PACKAGE TOP VIEW • EPIC (Enhanced-Performance Implanted 1CCR [ 1 1D [ 2 CMOS) Submicron Process • 1CLK [ 3 Designed to Facilitate Incident Wave

Contextual Info: SN54LVU04, SN74LVU04 HEX INVERTERS S C L S 1 B 5 B - FEBRUARY 1993 - REVISED APRIL 1996 EPIC Enhanced-Performance Implanted CMOS 2-n Process Typical V q l p (Output Ground Bounce) < 0.8 V at V c c . Ta = 25°C Typical V q h v (Output V q h Undershoot)

tlc27l41

Abstract: ac av hen eta
Contextual Info: TLC27L4, TLC27L4A, TLC27L4B, TLC27L9 LinCMOS PRECISION QUAD OPERATIONAL AMPLIFIERS D 3 1 42, O C T O B E R 1 9 8 7 - R E V I S E D O C T O B E R 1 9 9 0 • • • Trimmed Offset Voltage: TLC27L9 . . . 900 pM Max at 25 °C, Vd d - 5 V D, J, OR N PACKAGE

Contextual Info: SN54ALVTH16652, SN74ALVTH16652 2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCES192 - FEBRUARY 1999 State-of-the-Art Advanced BiCMOS Technology ABT Widebus Design for 2.5-V and 3.3-V Operation and Low Static-Power Dissipation

Contextual Info: SN74ACT7881 1024 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS227C - FEBRUARY 1993 - REVISED FEBRUARY 1996 • Member of the Texas Instruments Wldebus Family • Independent Asynchronous Inputs and Outputs • Input-Ready, Output-Ready, and Half-Full Flags

Contextual Info: 74ACT11132 QUADRUPLE POSITIVE-NAND GATE WITH SCHMITT-TRIGGER INPUTS SCAS177 - D3974, JANUARY 1992 - REVISED APRIL 1993 Inputs Are TTL-Voltage Compatible Center-Pin V^c and GND Pin Configurations Minimize High-Speed Switching Noise EP/C Enhanced-Performance Implanted