SCAS340 Search Results

Contextual Info: SN74LVC137 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER WITH ADDRESS LATCHES SCAS340 - MARCH 1994 » EPIC Enhanced-Performance Implanted CMOS Submicron Process • Typical V o lp (Output Ground Bounce) D, DB, OR PW PACKAGE (TOP VIEW) A[ B[ c[ Ü2A [ S2B[ G1[

SN74LVC137A

Contextual Info: SN74LVC137A 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER WITH ADDRESS LATCHES SCAS340E – MARCH 1994 – REVISED JUNE 1998 D D D D D EPIC Enhanced-Performance Implanted CMOS Submicron Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C

SN74LVC137A

Contextual Info: SN74LVC137A 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER WITH ADDRESS LATCHES SCAS340C – MARCH 1994 – REVISED JANUARY 1997 D D D D D EPIC Enhanced-Performance Implanted CMOS Submicron Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C

52axx

Contextual Info: SN74LVC137 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER WITH ADDRESS LATCHES SCAS340A-MARCH 1994 - REVISED JULY 1995 D, DB, OR PW PACKAGE TOP VIEW A[ B[ c[ 32A[ S2B [ u 1 2 3 4 5 G1 [ 6 Y7[ 7 GND [ 8 16 ] v cc 15 ] Y0 14 ]Y1 13 ]V2 12 ] Y3 11 ]Y4 10 ] Y 5 9 ] Y6

SCAS340

Contextual Info: CDC2351 1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS340- FEBRUARY 1994-REVISED MARCH 1994 DB OR DW PACKAGE TOP VIEW Low O utput Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications Operates at 3.3-V V c c LVTTL-Compatibie Inputs and Outputs

Contextual Info: SN74LVC137A 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER WITH ADDRESS LATCHES www.ti.com SCAS340E – MARCH 1994 – REVISED FEBRUARY 2005 FEATURES • • • • • D, DB, OR PW PACKAGE TOP VIEW EPIC (Enhanced-Performance Implanted CMOS) Submicron Process

Contextual Info: SN74LVC137 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER WITH ADDRESS LATCHES SCAS340 - MARCH 1994 D, DB, OR PW PACKAGE TOP VIEW EPIC (Enhanced-Performance Implanted CMOS) Submicron Process Typical Vo lp (Output Ground Bounce) < 0.8 V at Vc c = 3.3 V, TA = 25°C

TO8 package

Abstract: SN74LVC137A
Contextual Info: SN74LVC137A 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER WITH ADDRESS LATCHES www.ti.com SCAS340E – MARCH 1994 – REVISED FEBRUARY 2005 FEATURES • • • • • D, DB, OR PW PACKAGE TOP VIEW EPIC (Enhanced-Performance Implanted CMOS) Submicron Process

SN74 schmitt trigger

Abstract: SDYU001 SN54LV00A SN54LV02A SN54LV04A SN54LV05A SN54LV08A SN54LV14A SN54LV32A SN54LV74A
Contextual Info: LVC and LV LowĆVoltage CMOS Logic Data Book 1998 Logic Products General Information LVC Gates and MSI LVC Octals LVC Widebus LVC 3.3-V to 5-V Translators and Cable Drivers LV Gates and MSI LV Octals Application Reports Mechanical Data LVC and LV Low-Voltage CMOS Logic

LSK Series

Abstract: CDC2351
Contextual Info: CDC2351 1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS SC A S 340- FEBRUARY 1994 - REVISED MARCH 1994 DB OR DW PACKAGE TOP VIEW GND [ 1 u Y10 t 2 V Cc I 3 Y9[ 4 0E[ 5 A[ 6 P0[ 7 P1 [ 8 Y8 [ 9 V e c i 10 Y 7 l 11 G N D [ 12 24 23 22 21 20 19 18 17 16

transistor fn 1016

Abstract: SN74HC1G00 SCAD001D sn74154 SN74ALVC1G32 JK flip flop IC SDFD001B philips 18504 FB 3306 CMOS Data Book Texas Instruments Incorporated
Contextual Info: W O R L D L Logic Selection Guide August 1998 E A D E R I N L O G I C P R O D U C T S LOGIC OVERVIEW 1 FUNCTIONAL INDEX 2 FUNCTIONAL CROSSĆREFERENCE 3 DEVICE SELECTION GUIDE 4 3 LOGIC SELECTION GUIDE AUGUST 1998 IMPORTANT NOTICE Texas Instruments and its subsidiaries TI reserve the right to make changes to their products or