PL1C Search Results

B1568

Contextual Info: 55 Standard & mini-weco coax patch plugs Standard Mini-WECo .437 WRENCH FLATS .312 WRENCH FLATS , , , , , , 1.818 .375 DIA .946 B , , , , , , .298 A Patch Plug PL1C- 50Ω RCA Center pin .070" A=2.73" B=1.50" Shield Crimp

00XXX001

Abstract: BA 5979 R15C3 OR3T125 OR3T20 OR3T30 OR3T55 PT10 PT11 PT12
Contextual Info: Data Sheet November 2006 ORCA Series 3C and 3T Field-Programmable Gate Arrays Features • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Baseline FPGA family used in Series 3+ FPSCs field programmable system chips which combine FPGA logic

TA138

Abstract: A1240XL 32 Bit loadable counter 2 bit magnitude comparator 176-CPGA "alu 4 bit" IC LM 384 gn
Contextual Info: Æ ic t â 1200XL Field Programmable Gate Arrays Features • Up to 8000 Gate Array Gates 20,000 PLD equivalent gates Datapath Performance at 135 MHz • Replaces up to 200 TTL Packages 10 ns Clock-Out speeds • Replaces up to eighty 20-Pin PAL Packages

983-495 thermax

Abstract: bj3450 PL75C-201 m27500-22rc2s06 PL155AC-201 305-0042-1 EPD22030F M27500-26RC2S06 PL75MC ASNE 0094
Contextual Info: PRODUCT CATALOG Military, Space and Testing Equipment Emerson Network Power Connectivity Solutions has a wide range of cable assemblies and connectors suited for RF, Microwave and Fiber Optic signal transmission. Connectivity Solutions is a vertically integrated supplier of custom, fixed

OR3LP26B

Abstract: OR3T20 ORT8850 7ba2 diode pb7d
Contextual Info: Preliminary Data Sheet April 2001 PayloadPlus /APC UTOPIA Slave Bridge Introduction Features The PayloadPlus/ATM port controller APC universal test and operations PHY interface for ATM (UTOPIA) slave bridge, also known as the PayloadPlus APC wedge (PAW) or the Atlanta™ interface

Contextual Info: Features Datasheet RX64M Group Renesas MCUs R01DS0173EJ0100 Rev.1.00 Jul 31, 2014 120-MHz 32-bit RX MCU, on-chip FPU, 240 DMIPS, up to 4-MB flash memory, 512-KB SRAM, various communications interfaces including IEEE 1588-compliant Ethernet MAC, full-speed USB 2.0 with battery charging, SD host interface optional , quad SPI, and CAN, 12-bit A/D

Contextual Info: ST92F124/ST92F150/ST92F250 8/16-BIT SINGLE VOLTAGE FLASH MCU FAMILY WITH RAM, E3 TM EMULATED EEPROM , CAN 2.0B AND J1850 BLPD PRELIMINARY DATA • Memories – Internal Memory: Single Voltage FLASH up to 256 Kbytes, RAM up to 8Kbytes, 1K byte E 3 TM (Emulated EEPROM)

CONTROLLER

Abstract: speed control of three phase ac induction motor 3 phase ac Induction motor speed controller ic SPEED CONTROLLER FOR SMALL MOTOR WITH TACHOGENERATOR 220v dc motor speed control circuit 220v DC MOTOR SPEED CONTROLLER 220v DC MOTOR SPEED CONTROLLER schematic cmos XOR schmitt trigger pwm based bidirectional dc motor speed SCHEMATIC 12 to 220v inverter
Contextual Info: ST92141 8/16-BIT MCU FOR 3-PHASE AC MOTOR CONTROL • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Register File based 8/16 bit Core Architecture with RUN, WFI, SLOW, HALT and STOP modes 0-25 MHz Operation internal clock @ 5V±10%

ST90R91

Abstract: st90r9
Contextual Info: SGS-THOMSON ¡y ST90R91 ROMLESS HCMOS MCU WITH BANKSWITCH _ AND A/D CONVERTER PRELIMINARY DATA Register oriented 8/16 bit CORE with RUN, WFI and HALT modes Minimum instruction cycle time : 500ns 12MHz internal ROMIess to allow maximum external memory

Contextual Info: ORCA ORLI10G Quad 2.5Gbps, 10Gbps Quad 3.125Gbps, 12.5Gbps Line Interface FPSC August 2004 Data Sheet Introduction The Lattice ORCA Series 4-based ORLI10G FPSC combines a high-speed line interface with a flexible FPGA logic core. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the ORLI10G consists

ST92141

Abstract: ST92E141 ST92P141 ST92T141 electronic tubes
Contextual Info: ST92141 8/16-BIT MCU FOR 3-PHASE AC MOTOR CONTROL PRELIMINARY DATA • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Register File based 8/16 bit Core Architecture with RUN, WFI, SLOW, HALT and STOP modes 0-25 MHz Operation internal clock @ 5V±10%

Contextual Info: AT&T Data Sheet October 1995 Microelectronics Optimized Reconfigurable Cell Array ORCA 2C Series Field-Programmable Gate Arrays Features Description • High-performance, cost-effective 0.5 |im technology (four-input look-up table delay less than 3.6 ns)

IC TTL 7495 diagram and truth table

Abstract: BA 5979 S AM 5766 BA 5979 motorola s240 pin diagram of ic 7495 Xilinx counter transistor on 4409 PR25D inverter design using plc
Contextual Info: Data Sheet June 1999 ORCA Series 3C and 3T Field-Programmable Gate Arrays Features • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High-performance, cost-effective, 0.35 µm OR3C and 0.3 µm (OR3T) 4-level metal technology, (4- or 5-input look-up table delay of 1.1 ns with -7 speed grade in

PT35c transistor

Abstract: pt35c transistor pt36c me 4946 PBGA PR25D transistor on 4409 307-45 4946 ah lm 458 ic
Contextual Info: Data Addendum March 2002 ORCA OR3LxxxB Series Field-Programmable Gate Arrays Introduction This data addendum refers to the information found in the ORCA® Series 3C and 3T Field-Programmable Gate Arrays Data Sheet. • ■ Features ■ ■ ■ ■ ■ ■

HLX quartz

Abstract: ST6398 98 UTA ING LA 76811 LM 76811 ST90 xckp CQFP80 PLCC84 PQFP80
Contextual Info: 7 7 SGS-THOMSON 'JM, DfflDim@II[L[gOTa@raD g§ ST90158 - ST90135 8/16-BIT MCU FAMILY W ITH 16 to 64K ROM and 512 to 2K RAM P R E L IM IN A R Y D A T A • Register File based 8/16 bit Core Architecture with RUN, W FI, SLOW and HALT modes ■ 0 - 1 6 MHz Operation @ 5V±10%

Contextual Info: ST92163 8/16-BIT FULL SPEED USB MCU FOR COMPOSITE DEVICES WITH 16 ENDPOINTS, 20K ROM, 2K RAM, I2C, SCI, & MFT PRELIMINARY DATA • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Internal Memories: 20 Kbytes ROM/EPROM/ OTP, 2 Kbytes RAM

SS 1091 asn

Abstract: TDA 1045 picture in picture chip SAE-J1850
Contextual Info: ST92F120 8/16-BIT FLASH MCU FAMILY WITH RAM, EEPROM AND J1850 BLPD PRELIMINARY DATA • ■ ■ ■ Memories – Internal Memory: up to 128 Kbytes Single Voltage FLASH, 2 to 4 Kbytes RAM, 1K byte emulated EEPROM E3PROMTM – 224 general purpose registers (register file)

MARKING CODE N-CHANNEL MOS FIELD EFFECT TRANSISTOR

Abstract: nb 358 d
Contextual Info: ST92F124/ST92F150/ST92F250 8/16-BIT SINGLE VOLTAGE FLASH MCU FAMILY WITH RAM, E3 TM EMULATED EEPROM , CAN 2.0B AND J1850 BLPD PRELIMINARY DATA • Memories – Internal Memory: Single Voltage FLASH up to 256 Kbytes, RAM up to 8Kbytes, 1K byte E3 TM (Emulated EEPROM)

DAP 015

Contextual Info: ST92F120 8/16-BIT FLASH MCU FAMILY WITH RAM, EEPROM AND J1850 BLPD DATASHEET • ■ ■ ■ Memories – Internal Memory: up to 128 Kbytes Single Voltage FLASH, 2 to 4 Kbytes RAM, 1K byte emulated EEPROM E3PROMTM – 224 general purpose registers (register file)

7476 3 bit ripple counter

Abstract: 7464 shift register marking code IAM SDIP32 SDIP42 ST92186B fsa10as
Contextual Info: ST92186B 8/16-BIT MCU FOR TV APPLICATIONS WITH UP TO 32K ROM AND ENHANCED ON-SCREEN-DISPLAY • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Register file based 8/16 bit Core Architecture with RUN, WFI, and HALT modes -10 to 70°C Operating Temperature Range

BA 5979 S

Abstract: or3t806ba352-db 2764 EEPROM BA 5979 BL06 transistor OR3T125 OR3T20 OR3T30 OR3T55 PT10
Contextual Info: Data Sheet November 2006 ORCA Series 3C and 3T Field-Programmable Gate Arrays Features • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High-performance, cost-effective, 0.35 m OR3C and 0.3 μm (OR3T) 4-level metal technology, (4- or 5-input look-up table delay of 1.1 ns with -7 speed grade in

Contextual Info: ST92163R4 8/16-BIT FULL SPEED USB MCU FOR COMPOSITE DEVICES WITH 16 ENDPOINTS, 20K ROM, 2K RAM, I2C, SCI, & MFT NOT FOR NEW DESIGN • ■ ■ s t c u d o s) r ( P t c e u t e l od o s Pr b O ete l ) o s ( s t b c u -O d o s) r P ( t e uc t e l od o s Pr

1-256 demultiplexer

Contextual Info: ORCA ORLI10G Quad 2.5Gbps, 10Gbps Quad 3.125Gbps, 12.5Gbps Line Interface FPSC November 2003 Data Sheet Introduction Lattice has developed a new ORCA Series 4-based FPSC which combines a high-speed line interface with a flexible FPGA logic core. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the

PT15D

Abstract: OR2T40A-6PS208I R4C18
Contextual Info: Data Sheet August 2002 ORCA Series 2 Field-Programmable Gate Arrays Features • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High-performance, cost-effective, low-power 0.35 µm CMOS technology OR2CxxA , 0.3 µm CMOS technology (OR2TxxA), and 0.25 µm CMOS technology