1200XL Search Results

Actel A1225

Abstract: PL84 A1240XL actel a1240 A32140 PQ100C Cadence TQ176 PG176
Contextual Info: ^ c te l - w Integrator Series FPGAs: 1200XL and 3200DX Famüies Features a 4 L. ¡§ Cadence, Escalade, Exemplar, 1ST, Mentor Graphics, Synopsvs, and Viewlogic. High C a p a c ity • IEEE Standard 1149.1 JTAG Boundary Scan Testing.

TA138

Abstract: A1240XL 32 Bit loadable counter 2 bit magnitude comparator 176-CPGA "alu 4 bit" IC LM 384 gn
Contextual Info: Æ ic t â 1200XL Field Programmable Gate Arrays Features • Up to 8000 Gate Array Gates 20,000 PLD equivalent gates Datapath Performance at 135 MHz • Replaces up to 200 TTL Packages 10 ns Clock-Out speeds • Replaces up to eighty 20-Pin PAL Packages

Contextual Info: Integrator Series FPGAs - 1200XL and 3200DX Famüies Features Cadence, Escalade, Exemplar, 1ST, M entor Graphics, Synopsys and Viewlogic High C a p a c ity • JTAG1149.1 Boundary Scan Testing • 2,500 to 40,000 logic gates • Up to 4 Kbits configurable dual-port SRAM

actel fpga

Abstract: SIGNAL PATH designer
Contextual Info: Appl i cat i o n N ot e Designing for Migration to Actel MPGAs The Actel Mask Programmed Gate Array MPGA family of high-density, high-performance devices comprises mask programmed versions of the ACT 1, ACT 2, 1200XL, 3200DX, and ACT 3/ACT 3 PCI Field Programmable Gate Array

132-PIN CERAMIC PIN GRID ARRAY CPGA

Abstract: A3265DX Actel A1240 WD109 A1225XL A1240XL A1280XL A32100DX A32140DX A32200DX
Contextual Info: Integrator Series FPGAs – 1200XL and 3200DX Familes Features Cadence, Escalade, Exemplar, IST, Mentor Graphics, Synopsys and Viewlogic • JTAG 1149.1 Boundary Scan Testing High Capacity • • • • 2,500 to 40,000 logic gates Up to 4 Kbits configurable dual-port SRAM

GHL 8

Abstract: FPGA 144 CPGA 172 PLCC ASIC actel a1240 a1280xlf
Contextual Info: Integrator SeriesFPGAs: 1200XL and 3200DX Families Features Cadence, Escalade, E xem plar, 1ST, M e n to r G raphics, Synopsys, and V iew logic. High C a p a c i t y • • 2,500 to 40,000 Logic Gates • Up to 4 K b its C o n fig u ra b le D ual-Port SRAM

A42MX24

Abstract: AC297 ACTEL PQ160 CQFP 256 PIN actel A1280XL 42MX ACTEL A1240xl A32140DX PQ208 adb 230 CQ256
Contextual Info: Application Note AC297 Migrating from 1200XL and 3200DX to 42MX FPGAs Overview This application note provides the information needed for seamless migration of a design from the 1200XL and 3200DX families to the 42MX family. The Actel 42MX device architecture is based on the Actel 1200XL and 3200DX families; thus, it shares the

TA688

Abstract: 7input and gate ao1b AO11 TA164 TA-191 TA153 TA190 DLM8 TA273
Contextual Info: Integrator Series Macro Library – Tables of Hard, Soft, and TTL Macros Hard Macros—Combinatorial Modules Function Macro Description Combinatorial Logic Module CM8 Combinational Module Full 1200XL and 3200DX Logic Module Sequential Logic Module DFM7A

Actel a1280

Abstract: VKS FPGA CQFP 106 wd5080 74 series family A1280 A32200DX-RQ208 Actel A1225 A1225XL A1240XL A1280XL
Contextual Info: v3.0 Integrator Series FPGAs: 1200XL and 3200DX Families Fe a t ur es G en er al D e sc r i p t i on High C apaci t y Actel’s Integrator Series FPGAs are the first programmable logic devices optimized for high-speed system logic integration. Based on Actel’s proprietary antifuse

Actel a1280

Abstract: 240 pin rqfp drawing A1280 VKS FPGA CQFP 106 Actel A1225 172 pin leaded A1225XL CQ84 A1240XL A1280XL
Contextual Info: Discontinued – v3.0 v3.0 Integrator Series FPGAs: 1200XL and 3200DX Families F ea t u re s G e n e ra l D es c ri p t i o n H ig h C a p ac it y Actel’s Integrator Series FPGAs are the first programmable logic devices optimized for high-speed system logic

1225XL

Abstract: A1240XL LM 7447
Contextual Info: Prelim inary 1200X L Field Program m able G ate Arrays Features Description • The 1200XL family, Actel’s fourth family of field programmable gate arrays FPGAs , is targeted as a V A L U E family, offering very low costs and mid-to-high range performance. The 1200XL family

B12C3

Abstract: LA1240
Contextual Info: Integrator Series FPGAs - 1200XL and 3200DX Familes F e a tu re s Cadence, Escalade, Exemplar, 1ST, Mentor Graphics, Synopsys and Viewlogic H ig h C a p a c ity • JTAG 1149.1 Boundary Scan Testing • 2,500 to 40,000 logic gates • Up to 4 Kbits configurable dual-port SRAM

A1280XL

Abstract: rq20 A1225XL A1240XL A32100DX A32140DX A32200DX A32300DX A3265DX actel a1240
Contextual Info: Integrator Series FPGAs – 1200XL and 3200DX Familes Features Cadence, Escalade, Exemplar, IST, Mentor Graphics, Synopsys and Viewlogic • JTAG 1149.1 Boundary Scan Testing High Capacity • • • • 2,500 to 40,000 logic gates Up to 4 Kbits configurable dual-port SRAM

Contextual Info: I ntegrator Series FPGAs: 1200XL and 3200DX Families Features Cadence, Escalade, E xem plar, 1ST, M e n to r G raphics, Synopsys, and V iew logic. High C a p a c ity • • 2 ,5 0 0 1o 40,000 Logi c Gat es • Up to 4 K b its C o n fig u ra b le D ual-P ort SRAM

A1240XL

Abstract: actel a1240 CQFP 172 PIN A3265DX actel cqfp 84
Contextual Info: BACK Integrator Series FPGAs – 1200XL and 3200DX Familes Features Cadence, Escalade, Exemplar, IST, Mentor Graphics, Synopsys and Viewlogic • JTAG 1149.1 Boundary Scan Testing High Capacity • • • • 2,500 to 40,000 logic gates Up to 4 Kbits configurable dual-port SRAM

Actel a1225xl

Abstract: A1225XL A3265DX-2 AC106 SIGNAL PATH designer
Contextual Info: Application Note AC106 Fast On and Off Chip Delays with 1200XL and 3200DX I/O Latches Introduction Using Actel 1200XL and 3200DX devices, latched I/O buffer macros can improve clock input-to-registered-output performance. Latched I/O buffer macros also increase the

Contextual Info: Integrator Series FPGAs - 1200XL and 3200DX Familes Features Cadence, Escalade, Exemplar, 1ST, Mentor Graphics, Synopsys and Viewlogic H ig h C a p a c ity • JTAG 1149.1 Boundary Scan Testing • 2,500 to 40,000 logic gates • Up to 4 Kbits configurable dual-port SRAM

Actel a1225xl

Abstract: A3265DX-2 A1225XL SIGNAL PATH designer
Contextual Info: Appl i cat i o n N ot e Fast On and Off Chip Delays with 1200XL and 3200DX I/O Latches Introduction Using Actel 1200XL and 3200DX devices, latched I/O buffer macros can improve clock input-to-registered-output performance. Latched I/O buffer macros also increase the

A1280

Abstract: Actel A1225 Actel a1280 A1240XL A1225XL Datasheet Actel A1225A A1225 A1225A A1225A-2 A1240
Contextual Info: 1200XL DB DS Page 103 Tuesday, October 3, 1995 8:36 AM 1200XL Field Programmable Gate Arrays F e atures • Up to 8000 Gate Array Gates 20,000 PLD equivalent gates • Replaces up to 200 TTL Packages • Replaces up to eighty 20-Pin PAL Packages • Design Library with over 500 Macro Functions

verilog i2s

Abstract: verilog i2s bus
Contextual Info: Iintegrator Series FPGAs - 1200XLand 3200DXFamilies Features • JT A G 1149.1 Boundary Scan Testing • 2,500 to 40,000 logic gates • • Up to 4 Kbits configurable dual-port SRAM Fast wide-decode c irc u itry • Up to 288 user-programm able I/O Pins G eneral D escriptio n

actel 1240a

Abstract: TI1139 UI02 1280xl actel 1240xl 132 pga UJ-01 U1H-18 110E06 SI 1020A Actel A1225
Contextual Info: Actel Device Reliability Report Actel’s field programmable gate arrays FPGAs are currently available in five product families—ACT 1, ACT 2, 1200XL, 3200DX, and ACT 3. The ACT 1 family consists of the A1010 and A1020, which are 1200- and 2000-gate FPGAs,

ES50N18LA2

Abstract: YTX14-BS YTZ10S MOTORCYCLE engine specifications yamaha mt-03 ES14AA2 PT12B YTZ14s GL1800 EXIDE GEL G 210
Contextual Info: 145372_CalCoastAdv 2/23/11 4:07 PM Page 1 145372_CalCoastAdv 2/23/11 4:07 PM Page 2 Sealed Maintenance Free Battery Features Sealed Post Prevents acid leakage, reduces corrosion, and extends battery life safety valve flame/arrestor relieves excess pressure

Contextual Info: Com m ercial/Industrial D ev ice s PLCC 44 68 84 PQFP 100 144 160 208 240 RQFP 208 240 VQFP 80 TQFP 100 144 BGA 225 176 272 313 CPGA 329 84 100 132/133 175/176 207 257 CQFP 84 132 172 196 208 256 HiRel/Space D evice RadTolerant < o o 12 x CM CO X 5 A </

FP160

Contextual Info: 1-278 o o o o o o o o o o o o ov o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o