PK131 Search Results

IS41LV16257B

Abstract: 41LV16257B PK13197T40
Contextual Info: IS41LV16257B JUNE 2007 256K x 16 4-MBIT DYNAMIC RAM WITH FAST PAGE MODE FEATURES DESCRIPTION • • • • The ISSI IS41LV16257B is 262,144 x 16-bit highperformance CMOS Dynamic Random Access Memories. Fast Page Mode allows 512 random accesses within a single row with access cycle time as

IS61C5128AL

Abstract: IS61C5128AS-25QLI IS61C5128AL-10KLI IS61C5128AL-10TLI IS61C5128AS-25TLI 64C5128AS
Contextual Info: IS61C5128AL/AS IS64C5128AL/AS 512K x 8 HIGH-SPEED CMOS STATIC RAM FEATURES HIGH SPEED: IS61/64C5128AL • High-speed access time: 10ns, 12 ns • Low Active Power: 150 mW (typical) • Low Standby Power: 10 mW (typical) CMOS standby LOW POWER: (IS61/64C5128AS)

IS61LPD51236A

Abstract: IS61LPD102418A IS61VPD102418A IS61VPD51236A
Contextual Info: IS61VPD51236a IS61VPD102418a IS61lPD51236a IS61LPD102418a 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and

Contextual Info: m IS61SF12832 128K x 32 SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Fast access times: 7.5 ns, 8 ns, 8.5 ns, 10 ns, and 11 ns Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data inputs and control signals

Contextual Info: IS 6 1 C 6 3 2 A m s 32K x 32 SYNCHRONOUS PIPELINED STATIC RAM MAY 1998 FEATURES DESCRIPTION • Fast access time: The I S S I IS61C632A is a high-speed, low-power synchro­ nous static RAM designed to provide a burstable, highperformance, secondary cache for the i486 , Pentium™,

Contextual Info: ISSI IS29F010 1 MEGABIT 128K x 8-bit CMOS, 5.0V Only Sectored Flash Memory p r e l im in a r y O c t o b e r 1998 FEATURES • High-performance CMOS - 35, 45, 55, 70, and 90 ns max. access time • Single 5V-only power supply - 5V ± 10% for Read, Program, and Erase

Contextual Info: ISSI' IS 4 1 L V 1 6 2 5 6 256K x 16 4-MBIT DYNAMIC RAM WITH EDO PAGE MODE ADVANCE INFORMATION SEPTEMBER 1998 DESCRIPTION FEATURES Extended Data-Out (EDO) Page Mode access cycle LVTTL compatible inputs and outputs Single +3.3V ± 10% power supply 5V I/O tolerant

Contextual Info: m t IS 6 1 S P 6 4 6 4 64Kx 64 SYNCHRONOUS PIPELINE STATIC RAM FEATURES • Fast access time: - 5 ns-100 MHz; 6 ns-83 MHz; 7 ns-75 MHz; 8 ns-66 MHz • Internal self-tim ed w rite cycle • Individual Byte W rite Control and Global W rite • C lock controlled, registered address, data and

Contextual Info: I S 2 2 C ¡SSI 1 1 1 8 to 12 SEC VOICE ROM ADVANCE INFORMATION SEPTEMBER 1997 FEATURES • Voice length at: - 8 KHz sampling is 8 seconds - 6 KHz sampling is 10 seconds - 5 KHz sampling is 12.8 seconds • Silence compression saves memory • Four trigger pins, S1 to S4 for eight sections

IS41LV16105A

Contextual Info: ISSI IS41LV16105A 1M x 16 16-MBIT DYNAMIC RAM WITH FAST PAGE MODE APRIL 2005 FEATURES DESCRIPTION • TTL compatible inputs and outputs; tristate I/O The ISSI IS41LV16105A is 1,048,576 x 16-bit high-performance CMOS Dynamic Random Access Memories. Fast Page

IS61LPD102418A

Abstract: IS61LPD51236A IS61VPD102418A IS61VPD51236A
Contextual Info: ISSI IS61VPD51236A IS61VPD102418A IS61LPD51236A IS61LPD102418A 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and

IS61LPS102418A

Abstract: IS61LPS25672A IS61LPS51236A IS61VPS102418A IS61VPS25672A IS61VPS51236A IS61LPS51236A-200TQLI 1024Kx18
Contextual Info: IS61VPS25672A IS61LPS25672A IS61VPS51236A IS61LPS51236A IS61VPS102418A IS61LPS102418A ISSI 256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write

IS62WV1288BLL-55HLI

Abstract: IS62WV1288ALL IS62WV1288ALL-70BI IS62WV1288ALL-70HI IS62WV1288BLL IS62WV1288BLL-45TI
Contextual Info: IS62WV1288ALL IS62WV1288BLL ISSI 128K x 8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM JUNE 2005 FEATURES DESCRIPTION • High-speed access time: 45ns, 55ns, 70ns The ISSI IS62WV1288ALL / IS62WV1288BLL are highspeed, 1M bit static RAMs organized as 128K words by 8

IS41C16105

Abstract: IS41LV16105 IS41C16105-50TL N-40A
Contextual Info: IS41C16105 IS41LV16105 ISSI 1M x 16 16-MBIT DYNAMIC RAM WITH FAST PAGE MODE DECEMBER 2005 FEATURES DESCRIPTION • TTL compatible inputs and outputs; tristate I/O The ISSI IS41C16105 and IS41LV16105 are 1,048,576 x 16-bit high-performance CMOS Dynamic Random Access Memories. Fast Page Mode allows 1,024 random accesses within a single

IS61LPS25632A

Abstract: IS61LPS25636A IS61LPS51218A IS61VPS25636A IS61VPS51218A
Contextual Info: IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A, IS61VPS51218A, IS61VPS25636A 256K x 36, 256K x 32, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, Single CYCLE DESELECT STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write

IR-021

Contextual Info: ISSI IS61VPD51236A IS61VPD102418A IS61LPD51236A IS61LPD102418A 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and

Contextual Info: IS61NLF12836A/IS61NVF12836A IS61NLF25618A/IS61NVF25618A 128K x 36 and 256K x 18 4Mb, FLOW THROUGH 'NO WAIT' STATE BUS SRAM MAY 2007 FEATURES DESCRIPTION • 100 percent bus utilization The 4 Meg 'NLF/NVF' product family feature high-speed, low-power synchronous static RAMs designed to provide

Contextual Info: ISSI IS61LV256 32K x 8 LOW VOLTAGE CMOS STATIC RAM April 2004 FEATURES • High-speed access times: - 8, 10, 12, 15 ns • Automatic power-down when chip is deselected • CMOS low power operation - 345 mW max. operating - 7 mW (max.) CMOS standby

Contextual Info: IS63LV1024 IS63LV1024L ISSI 128K x 8 HIGH-SPEED CMOS STATIC RAM 3.3V REVOLUTIONARY PINOUT MAY 2004 FEATURES DESCRIPTION • High-speed access times: 8, 10, 12 ns • High-performance, low-power CMOS process • Multiple center power and ground pins for

Contextual Info: IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A, IS61VPS51218A, IS61VPS25636A 256K x 36, 256K x 32, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, Single CYCLE DESELECT STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write

Contextual Info: IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE 'NO WAIT' STATE BUS SRAM ISSI FEBRUARY 2005 FEATURES DESCRIPTION • 100 percent bus utilization The 18 Meg 'NLP/NVP' product family feature high-speed,

MAX714

Contextual Info: IS5F ¡ IB 131,072 x 16/262,144 x 8 SmartVoltage BOOT BLOCK FLASH MEMORY • SmartVoltage Technology — 5V or 12V Program/Erase — 2.7V, 3.3V or 5V Read Operation ADVANCE INFORMATION JULY 1997 Industrial Temperature Operation 40°C to +85°C • High-Performance Read

8-Pin JEDEC Small Outline "GR"

Contextual Info: ISSI 4,096-BIT SERIAL ELECTRICALLY ERASABLE PROM APRIL 1997 FEATURES OVERVIEW • State-of-the-art architecture — Non-volatile data storage — Low voltage operation: 3.0V Vcc = 2.7V to 6.0V — Full TTL compatible inputs and outputs — Auto increment for efficient data dump

Contextual Info: IS61NLP25636A/IS61NVP25636A IS61NLP51218A/IS61NVP51218A 256K x 36 and 512K x 18 9Mb, PIPELINE 'NO WAIT' STATE BUS SRAM ISSI PRELIMINARY INFORMATION JANUARY 2005 FEATURES DESCRIPTION • 100 percent bus utilization The 9 Meg 'NLP/NVP' product family feature high-speed,