PBSRAM Search Results

433 MHz RrF module 3 pin 5v

Abstract: processor pentium 1
Contextual Info: intei 1. MOBILE PENTIUM Il PROCESSOR AT 233 MHZ AND 266 MHZ INTRODUCTION cache the first 512 Mbytes of memory using a 512Kbyte cache data array composed of PBSRAMs. The private L2 cache bus complements the system bus by providing critical data faster, improving performance,

PBSRAM

Abstract: 71V576
Contextual Info: Integrated Device Technology, Inc. 2975 Stender Way, Santa Clara, CA - 95054 PRODUCT/PROCESS CHANGE NOTICE PCN PCN #: SR-0201-01 DATE: 2/8/02 MEANS OF DISTINGUISHING CHANGED DEVICES: Product Affected: 4M PBSRAM 71V576 Family - refer to attached list of part numbers.

Silicon-Based Technology

Contextual Info: SB61S64K64A Silicon-BasedTechnology Ultra High-Speed PBSRAM 64Kx 64 SYNCHRONOUS PIPELINED-BURST CMOS SRAM Preliminary FEATURES: Single 3.3V -5% and +10% power supply Fast clock access time: 3.75ns/133MHz , 4ns/125MHz , 5ns/100MHz Two clocked chip enable/one clocked chip disable

Contextual Info: SB61S128K64A Silicon-BasedTechnology Ultra High-Speed PBSRAM 128Kx 64 SYNCHRONOUS PIPELINED-BURST CMOS SRAM Preliminary FEATURES: Single 3.3V -5% and +10% power supply Fast clock access time: 3.75ns/133MHz , 4ns/125MHz , 5ns/100MHz Two clocked chip enable/one clocked chip disable

RAS 1210 SUN HOLD

Abstract: sun hold ras 1210 SiS5571 magnetic switch diagram push botton SiS chipset IRQ1-15 t85 ha6 HA2311 Silicon Integrated System HA25
Contextual Info: SiS5571 Pentium PCI/ISA Chipset 1. System Block Diagram PBSRAM CPU Host A ddress Host Data Bus Tag RAM MD Bus Master IDE MA Bus SiS5571 Keyboard DRAM USB PCI Bus ISA Bus ISA Device ISA D ev ice ISA Device Preliminary V2.0 December 9, 1996 ISA Device PCI Device

CY7C1395V25

Contextual Info: 395 CY7C1395 CY7C1395V25 PRELIMINARY 2M x36 PBSRAM with NoBL -Burst Architecture Features to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1395V25 operates with a 2.5V power supply and the CY7C1395 operates

PBSRAM

Abstract: mosys GW 66 475 ci 94086 MC80364K64 64KX64
Contextual Info: MC80364K64 Low Power 3.3V/2.5V MOSYS 64Kx64 PBSRAM • High performance, low power pipeline burst SRAM Ultra low power single chip 512Kbyte Cache for green PC and battery powered PC VSSQ - 39 N/C - 40 MODE - 41 A15 - 42 A14 - 43 A13 - 44 VDD - 45 VSS - 46

Contextual Info: 64K X 32 Fusion Memory SYNCHRONOUS CACHE RAM FEATURES: . performance of SRAM with the cost structure of DRAM. It is fundamentally compatible with standard PBSRAM, with addi­ tional features to accommodate the internal DRAM operation of the memory. These additional features are defined so that

IDT71F432

Abstract: IDT71F432S66 IDT71F432S75
Contextual Info: PRELIMINARY IDT71F432 32K x 32 Fusion Memory SYNCHRONOUS PIPELINED CACHE RAM Integrated Device Technology, Inc. FEATURES: performance of SRAM with the cost structure of DRAM. It is fundamentally compatible with standard PBSRAM, with additional features to accommodate the internal DRAM operation

VT82C686A

Abstract: 5133S TAG 064 USB audio codec DDC Panel floppy amplifier 352ac NS97338 socket 7 BGA492
Contextual Info:
 5133S System Block Diagram SOCKET 7 CPGA 321 HA[3.19] 32K*8 TAG RAM CRT LCD   HD[0.64] HA[3.19] Panel 64K*64 PBSRAM PCI 1211 PQFP 144 TPS2206 SSOP 16 AD[0.31] Control PCMCIA CONTROLLER TAG[0.7] Control Control CBI 7 MD[0.63] BGA 492 MA[0.13] SDRAM

5133S

Abstract: north bridge
Contextual Info:
 MODEL : 5133S Revision 02A Table of Contents Title Page Cover Sheet 1 Block Diagram 2 Central Processor Unit 3 North Bridge Part A & PBSRAM/TAG RAM 4   North Bridge Part B 5 System Memory 6 South Bridge 7 PCMCIA Controller & Socket 8 Audio Codec & Amplifier

SB61S64K64A-4

Abstract: SB61S64K64A-5
Contextual Info: SB61S64K64A Silicon-BasedTechnology Ultra High-Speed PBSRAM 64Kx 64 SYNCHRONOUS PIPELINED-BURST CMOS SRAM Preliminary FEATURES: •Single ■Synchronous ■Fast 3.3V -5% and +10% power supply clock access time: 3.75ns/133MHz , 4ns/125MHz , 5ns/100MHz ■Two clocked chip enable/one clocked chip disable

SB61S128K64A-5

Contextual Info: SB61S128K64A Silicon-BasedTechnology Ultra High-Speed PBSRAM 128Kx 64 SYNCHRONOUS PIPELINED-BURST CMOS SRAM Preliminary FEATURES: •Single ■Synchronous pipelined-operation 3.3V -5% and +10% power supply ■Internally self-timed WRITE cycle clock access time:

W22C

Abstract: S12301DS 5133S stp520 t12m256 T12M256A-12J UPC507 MITAC PC515 GP014
Contextual Info: MODEL : 5133S Revision 02A Table of Contents page 1 Cover Sheet Block Diagram 2 Central Processor Unit 3 North Bridge Part A & PBSRAM/TAG RAM 4 North Bridge Part B 5 System Memory 6 South Bridge 7 PCMCIA Controller & Socket 8 Audio Codec & Amplifier 9 Enhance IDE & FDD Connector

non interruptible and burst and memory

Abstract: CY7C1395V25
Contextual Info: CY7C1395 CY7C1395V25 PRELIMINARY 2M x 36 PBSRAM with NoBL-Burst Architecture Functional Description • Pin-compatible to ZBT™ and NoBL™ devices • Supports up to166-MHz bus operations with zero wait states — Data is transferred on every clock • Internally self-timed output buffer control to eliminate

SiS 651 chipset

Abstract: SiS chipset TI HA04 logic diagram of 74LS245 SIS 651 128m simm 72 pin ide hardisk sis chipset ide pci to isa bridge Silicon Integrated System
Contextual Info: SiS5120 Pentium PCI/ISA Chipset 1. Introduction PBSRAM CPU Host Address Host Data Bus Tag RAM MD Bus 244 x 2 optional MA Bus Master IDE DRAM SiS5120 USB GPIO BIOS KBC 245 x2 or x4 PCI Bus ISA Bus ISA Device ISA Device ISA Device ISA Dev ice PCI Device PCI

QDR cypress

Abstract: QDR cypress burst of two Cypress QDR
Contextual Info: Quad Data RateTM SRAM QDRTM QDR RAMs and Quad Data Rate comprise a new family of products developed by Cypress Semiconductor, IDT, Inc. and Micron Technology 1 Evolution of Synchronous SRAM • PBSRAMs were designed for use as an L2 cache for processors – Optimized for long bursts of Reads or Writes

MoSys

Abstract: MC803128K32 pipeline burst
Contextual Info: MC803128K32 128Kx32 Pipeline Burst SRAM MOSYS • High performance, low power pipeline burst SRAM Overview The MoSys MC803128K32 is a high performance, low power pipeline-burst-SRAM PBSRAM . Fabricated using an advanced low power, high performance CMOS process, the MoSys MC803128K32 is

Contextual Info: 32K x 32 Fusion Memory SYNCHRONOUS PIPELINED CACHE RAM FEATURES: performance of SRAM with the cost structure of DRAM. It is fundamentally compatible with standard PBSRAM, with addi­ tional features to accommodate the internal DRAM operation of the memory. These additional features are defined so that

Ternary CAM

Abstract: AN-270 PBSRAM
Contextual Info: Preliminary Information IDT75T43100 IP Co-PROCESSOR 32K Entries Features Abstract ◆ The IDT75T43100 is designed to be used in applications that require high speed data searching such as routers, high layer switching and applications involved in the convergence of voice, data and video.

TA1307P

Abstract: TB62715FN TC7SZ00AFE 017V 8L85
Contextual Info: 東芝半導体情報誌アイ 1999 7月号 発行/（株）東芝 セミコンダクター社 電子デバイス営業事業部 営業企画部 TEL. 03-3457-3453 FAX. 03-5444-9431 c mi Se CONTENTS INFORMATION 設計期間を最大で90％以上短縮 マイコンの自動設計システムを米国メンター社と共同開発

92H-System

Abstract: 640T amd 15h power AMD-645 keyboard controller 1244H 07H-06H AMD k86
Contextual Info: AMD-640 TM Chipset BIOS Design Application Note 1997 Advanced Micro Devices, Inc. All rights reserved. Advanced Micro Devices, Inc. "AMD" reserves the right to make changes in its products without notice in order to improve design or performance characteristics.

SRAM 6116

Abstract: 5333-02 75P52100 IDT75P52100 ternary content addressable memory ternary
Contextual Info: Datasheet Brief 75P52100 IP Co-Processor 64K Entries Block Diagram Device Description IDT’s 75P52100 IPC is a high performance pipelined low-power, synchronous full-ternary 64K x 72 entry device. Each entry location in the IPC has both a Data entry and an associated Mask entry. IDT’s IPC

TC55V2377AFF-250

Abstract: tc55v2377 TC55V2377AFF-225 XX11X 1029-CH TC55V2377AFF
Contextual Info: TO SH IBA TC55V2377AFF-205,-225,-250 TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 65,536-WORD BY 36-BIT SYNCHRONOUS PIPELINED BURST STATIC RAM DESCRIPTION The TC55V2377AFF is a 2,359,296-bit synchronous pipelined burst static random access memory SRAM