O192 Search Results

A12L

Abstract: A14L IDT70V3579 IDT70V3579S
Contextual Info: HIGH-SPEED 3.3V 32K x 36 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM Features: ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access – Commercial: 5/6ns max. Pipelined output mode

d4184

Abstract: transistor N14 193 atmel application note AT6002 AT6003 AT6005 AT6010
Contextual Info: Features • High-performance • • • • • • • • • – System Speeds > 100 MHz – Flip-flop Toggle Rates > 250 MHz – 1.2 ns/1.5 ns Input Delay – 3.0 ns/6.0 ns Output Delay Up to 204 User I/Os Thousands of Registers Cache Logic Design

5d3 diode

Abstract: 6B15 7b12 MACH Programmer transistor 7B12 2D15 PAL 007 A power generator control circuit schematic 1C12 5D10
Contextual Info: MACH 5 CPLD Family I MAC ncludes H Adv anc 5A Fam e In form ily atio n Fifth Generation MACH Architecture FEATURES ◆ High logic densities and I/Os for increased logic integration ◆ ◆ ◆ ◆ ◆ ◆ ◆ — 128 to 512 macrocell densities — 68 to 256 I/Os

ic 4040

Abstract: 4040 cmos ci 4040 cmos 4040 stv 4325 O129-O135 PD16707 4040
Contextual Info: お客様各位 カタログ等資料中の旧社名の扱いについて 2010 年 4 月 1 日を以って NEC エレクトロニクス株式会社及び株式会社ルネサステクノロジ が合併し両社の全ての事業が当社に承継されております。従いまして、本資料中には旧社

Contextual Info: 1 MACH 5 FAMILY MACH 5 Family Fifth Generation MACH Architecture DISTINCTIVE CHARACTERISTICS ◆ ◆ ◆ ◆ ◆ ◆ ◆ Publication# 20446 Amendment/0 Rev: D Issue Date: August 1997 MACH 5 Family ◆ Fifth generation MACH architecture — 100% routable

dual-port RAM

Abstract: AT17 AT17LV010-10DP AT40K MQFPF256 IO358
Contextual Info: Features • Functionally and Pin Compatible with the Atmel Commercial and Military AT40K Series • Ultra High Performance • • • • • • • • • • • • • • – System Speeds 60 MHz – Array Multipliers > 32 MHz – 18 ns Flexible SRAM

CY37512

Abstract: CY37512V
Contextual Info: Back PRELIMINARY CY37512V UltraLogic 3.3V 512-Macrocell ISR™ CPLD — tPD = 15 ns Features • 512 macrocells in 32 logic blocks • 3.3V In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming — Design changes don’t cause pinout changes

CABGA

Abstract: fpga JTAG Programmer Schematics AT17 AT40K AT94K AT94S AT94S05AL AT94S10AL AT94S40AL C16107
Contextual Info: Features • Multichip Module Containing Field Programmable System Level Integrated Circuit • • • • • • • • • • • • • • • • • FPSLIC and Secure Configuration EEPROM Memory 512 Kbits to 1 Mbit of Configuration Memory with Security Protection and In-System

gck451

Abstract: 2818C AT40K AT40K05AL AT40K10AL AT40K20AL AT40K40AL AT40KAL XC4000 XC5200
Contextual Info: Features • Ultra High Performance • • • • • • • • • • – System Speeds to 100 MHz – Array Multipliers > 50 MHz – 10 ns Flexible SRAM – Internal Tri-state Capability in Each Cell FreeRAM – Flexible, Single/Dual Port, Synchronous/Asynchronous 10 ns SRAM

max 8770

Abstract: MOS 6526 SR299 diode 3562 SR300 IC 6994 14 pin SR300 datasheet what is product ON 4914
Contextual Info: PRELIMINARY PRODUCT INFORMATION MOS INTEGRATED CIRCUIT µ PD16708 300-OUTPUT TFT-LCD GATE DRIVER DESCRIPTION The µ PD16708 is a TFT-LCD gate driver equipped with 300-output lines. It can output a high-gate scanning voltage in response to CMOS level input because it provided with a level-shift circuit inside the IC circuit.

O2-A2

Abstract: Lattice Mach OX2 VCCIO11 ispMACH M4A3 M4A5-192 application note PAL 007 O64i
Contextual Info: ispMACH 4A CPLD Family High Performance E2CMOS In-System Programmable Logic FEATURES ◆ High-performance, E2CMOS 3.3-V & 5-V CPLD families ◆ Flexible architecture for rapid logic designs ◆ ◆ ◆ ◆ ◆ ◆ ◆ — Excellent First-Time-FitTM and refit feature

Contextual Info: Features • Multichip Module Containing Field Programmable System Level Integrated Circuit • • • • • • • • • • • • • • • • FPSLIC and Secure Configuration EEPROM Memory 512 Kbits to 1 Mbit of Configuration Memory with Security Protection and In-System

CY37512P208-100UMB

Abstract: CY37512P208-100UM CY37032VP44-100AI CY37256P160-83UM CY37064P44-154YMB CY37256P160-125UMB CERAMIC leaded CHIP CARRIER CLCC 68
Contextual Info: Family PRELIMINARY Ultra37000 CPLD Family 5V, 3.3V, ISR™ High-Performance CPLDs Features General Description • In-System Reprogrammable ISR™ CMOS CPLDs — JTAG interface for reconfigurability — Design changes don’t cause pinout changes — Design changes don’t cause timing changes

CY37032VP44-100AI

Abstract: CY37064P44-154YMB CY37512P208-100UMB
Contextual Info: Family Ultra37000 CPLD Family 5V, 3.3V, ISR™ High-Performance CPLDs Features General Description • In-System Reprogrammable™ ISR™ CMOS CPLDs — JTAG interface for reconfigurability — Design changes don’t cause pinout changes — Design changes don’t cause timing changes

74287

Abstract: ML9461B
Contextual Info: FEDL9461-01 Issue Date: Jan 29, 2009 ML9461B Segment Driver for Dot Matrix STN Liquid Crystal Display 1. Product Overview 1.1 General Description The ML9461B is a 320-output segment driver for driving a dot matrix LCD panel. The driver enables switching between 320 outputs and 240 outputs and 200 outputs. The ML9461B is used in

Contextual Info: ispMACH 4A CPLD Family High Performance E2CMOS In-System Programmable Logic FEATURES ◆ High-performance, E2CMOS 3.3-V & 5-V CPLD families ◆ Flexible architecture for rapid logic designs ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ — Excellent First-Time-FitTM and refit feature

O2-A2

Abstract: C10C8
Contextual Info: ispMACH 4A CPLD Family High Performance E2CMOS In-System Programmable Logic FEATURES ◆ High-performance, E2CMOS 3.3-V & 5-V CPLD families ◆ Flexible architecture for rapid logic designs ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ — Excellent First-Time-FitTM and refit feature

MCF5272

Abstract: MPC860T ic tea 2025 PQFP 80 14 0.65 MCF5272UM
Contextual Info: MCF5272 ColdFire Integrated Microprocessor User’s Manual MCF5272UM/D Rev. 0, 02/2001 ColdFire is a registered trademark and DigitalDNA is a trademark of Motorola, Inc. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty,

tico 732

Abstract: TEA1012 CALIFORNIA MICRO DEVICES catalog O2 micro
Contextual Info: PRELIMINARY The MACH 5 Family Fifth Generation MACH Architecture V A N T I S The Programmable Logic Company From AMD DISTINCTIVE CHARACTERISTICS • Fifth generation MACH architecture — 100% routable — 5-V devices will not overdrive 3-V inputs safe for

tl o84

Abstract: AT60054QI fyl 5042 ugc m6 90 v-0 tl o71 TL O74 AT6002 AT6003 AT6005 AT6010
Contextual Info: AT6000 Series Features • • • • • • • High Performance System Speeds > 100 MHz Flip-Flop Toggle Rates > 250 MHz 1.2 ns Input Delay 3.5 ns Output Delay Thousands of Registers Cache Logic Design Complete/Partial In-System Reconfiguration No Loss of Data or Machine State

SDS S4 24V

Abstract: transistor s97 PD160300 s189 transistor s99 uPD160300 S187 S190 LE-12T solder s96
Contextual Info: PRELIMINARY PRODUCT INFORMATION MOS INTEGRATED CIRCUIT µPD160300 192-BIT AC-PDP DRIVER DESCRIPTION The µ PD160300 is a high-withstanding-voltage CMOS driver designed for use with a flat display panel such as a PDP, VFD, or EL panel. It consists of a 192-bit bi-directional shift register, 192-bit latch and high-withstanding-voltage

TQFP-144 footprint

Abstract: AT40K AT40K05AL AT40K10AL AT40K20AL AT40K40AL AT40KAL XC4000 XC5200 PQFP 352
Contextual Info: Features • Ultra High Performance • • • • • • • • • – System Speeds to 100 MHz – Array Multipliers > 50 MHz – 10 ns Flexible SRAM – Internal Tri-state Capability in Each Cell FreeRAM – Flexible, Single/Dual Port, Synchronous/Asynchronous 10 ns SRAM

PD16652TFT-LCD

Abstract: O200 SR200 2450-11 C982 SR199
Contextual Info: データ・シート MOS集積回路 MOS Integrated Circuit µ PD16652 200/192出力TFT-LCD用ゲート・ドライバ µ PD16652は，TFT-LCD用ゲート・ドライバです。また，ロジック入力にレベル・シフト回路を内蔵しています

A12L

Abstract: A13L IDT70V3569 IDT70V3569S "Dual-Port RAM"
Contextual Info: HIGH-SPEED 3.3V 16K x 36 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM Features: ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access – Commercial: 5/6ns max. Pipelined output mode