NON-PIPELINED PROCESSOR Search Results

Contextual Info: LAN91C96 Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet Product Features Non-PCI Single-Chip Ethernet Controller Pipelined Data Path A Subset of Motorola 68000 Bus Interface Support Handles Block Word Transfers for any Alignment

68000 mmu

Abstract: LAN91C96 mt 68000 LAN91C96-MS
Contextual Info: LAN91C96 Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet Product Features ƒ Non-PCI Single-Chip Ethernet Controller ƒ Pipelined Data Path ƒ A Subset of Motorola 68000 Bus Interface Support ƒ Handles Block Word Transfers for any

Contextual Info: LAN91C96 Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Datasheet Product Features ƒ Non-PCI Single-Chip Ethernet Controller ƒ Pipelined Data Path ƒ A Subset of Motorola 68000 Bus Interface Support ƒ Handles Block Word Transfers for any

Contextual Info: intei A D W M C B O M IF Û fô G M T tM M82370 INTEGRATED SYSTEM PERIPHERAL Programmable Walt State Generator — 0 to 15 Wait States Pipelined — 1 to 16 Wait States Non-Pipelined High Performance 32-Blt DMA Controller for 16-Bit Bus — 16 MBytes/Sec Maximum Data

G530T

Contextual Info: •HYUNDAI H Y 6 7 1 6 1 1 0 / 1 Ì 1 64K X 16 Bit SYNCHRONOUS CMOS SRAM PRELIMINARY DESCRIPTION This device integrates high-speed 64Kx16 SRAM core, address registers, data input registers, a 2-bit burst address counter and Non-pipelined output. All synchronous inputs pass through registers controlled by a

Contextual Info: H Y 6 7 V 1 6 1 1 0 /1 1 1 HYUNDAI 64K x 16 Bit SYNCHRONOUS CMOS SRAM PRELIM INARY DESCRIPTION This device integrates high-speed 64Kx16 SRAM core, address registers, data input registers, a 2-bit burst address counter and Non-pipelined output. All synchronous inputs pass through registers controlled by a

Contextual Info: H Y 6 7 V 1 8 1 1 0 /1 1 1 64K X 18 Bit SYNCHRONOUS CMOS SRAM -HYUNDAI PRELIMINARY DESCRIPTION This device integrates high-speed 64K x18 SRAM core, address registers, data input registers, a 2-bit burst ad­ dress counter and Non-pipelined output. All synchronous inputs pass through registers controlled by a positiveedge triggered clock K .

Contextual Info: MOTOROLA Freescale Semiconductor, Inc. Order this document by MCM63P631A/D SEMICONDUCTOR TECHNICAL DATA MCM63P631A Product Preview Freescale Semiconductor, Inc. 64K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM The MCM63P631A is a 2M bit synchronous fast static RAM designed to provide a burstable, high performance, secondary cache for the 68K Family, PowerPC, and Pentium microprocessors. It is organized as 64K words of 32 bits

MCM69F536C

Abstract: MCM69F536CTQ10 MCM69F536CTQ12 MCM69F536CTQ8 MCM69F536CTQ8R MCM69F536CTQ9 MCM69F536CTQ9R
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA 32K x 36 Bit Flow–Through BurstRAM Synchronous Fast Static RAM The MCM69F536C is a 1M–bit synchronous fast static RAM designed to provide a burstable, high performance, secondary cache for the 68K Family, PowerPC, 486, i960, and Pentium microprocessors. It is organized as 32K

Contextual Info: 0 M IF IR IfflM D @ R 9 in te i 82395DX HIGH PERFORMANCE SMART CACHE Optimized Intel386 DX Microprocessor Companion Concurrent Line Buffer Cacheing Multiprocessor Support Integrated 16KB Data RAM Expandable - up to 64KB 4 Way SET Associative with Pseudo

82395DX

Abstract: cr 5228 t intel 82395 82395 DMLF 164 weitek sd21, phi intel 82385 29038 weitek 3171
Contextual Info: in te i 82395DX HIGH PERFORMANCE SMART CACHE Optimized intel386TM DX Microprocessor Companion Concurrent Line Buffer Cacheing Integrated 16KB Data RAM Expandable - up to 64KB Supports lntel486TM Microprocessor­ like Burst Multiprocessor Support 4 Way SET Associative with Pseudo

Contextual Info: HY5216256 Series -HYUNDAI 256Kx 16-bit Video RAM with 2CAS Introduction Overview The 4megabit Video RAM is an application specific memory device designed for graphics applications. It comprises a 256k x16 DRAM memory array interfaced to a 256 x16 Serial Access Memory SAM , or register.

80960CA

Abstract: Non-Pipelined Single-Cycle processor 80960CA-16 80960CA-25 270710
Contextual Info: SPECIAL ENVIRONMENT 80960CA-25 -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR  Two Instructions Clock Sustained Execution  Four 59 Mbytes s DMA Channels with Data Chaining  Demultiplexed 32-bit Burst Bus with Pipelining Y 32-bit Parallel Architecture Two Instructions clock Execution

Contextual Info: Intel 80960CA-33, -25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR • Two Instructions/Clock Sustained Execution • Four 59 Mbytes/s DMA Channels with Data Chaining • Dem ultiplexed 32-bit Burst Bus with Pipelining • 32-bit Parallel Architecture — Two Instructions/clock Execution

25P010

Contextual Info: o Preliminary W25P010A Mnbond Electronics Corp. 32K x 32 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM GENERAL DESCRIPTION The W 2 5 P 0 1 0 A is a high-speed, synchronous-burst-pipelined, low-power C M O S static RAM organized as 32 ,768 x 3 2 bits that operates on a single 3.3-volt power supply. A built-in two-bit burst address

GEP2C02

Abstract: GES0016
Contextual Info: GES0016 16-Port, 32Gbps Configurable Switch Fabric Paion GES0016 Switch Fabric The Paion GES0016 is one of a powerful new series of high-performance chips from Paion. OEMs can use them to build state-of-the-art Fast Ethernet/Gigabit Ethernet switches. The chips work together in a variety of configurations with

Contextual Info: 80960CA-33, -25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR • • Two Instructions/Clock Sustained Execution Four 59 Mbytes/s DMA Channels with Data Chaining • Demultiplexed 32-bit Burst Bus with Pipelining • 32-bit Parallel Architecture — Two Instructions/clock Execution

MCM63P733A

Abstract: MCM63P733ATQ100 MCM63P733ATQ117 MCM63P733ATQ133 MCM63P733ATQ150 MCM63P733ATQ90 SCM63P733A SCM63P733ATQ133 motorola cmos scm
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA 128K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM The MCM63P733A and SCM63P733A are 4M–bit synchronous fast static RAMs designed to provide a burstable, high performance, secondary cache. The MCM63P733A and SCM63P733A organized as 128K words by 32 bits

Contextual Info: intJ. 80960CA-33, -25, -16 32-BIT HIGH PERFORMANCE EMBEDDED PROCESSOR • Two Instructions/Clock Sustained Execution • Four 59 Mbytes/s DMA Channels with Data Chaining • Demultiplexed 32-Bit Burst Bus with Pipelining • 32-bit Parallel Architecture — Two instructions/clock Execution

ib17

Contextual Info: M D M M ! 0 M [F © [s ]ß M ? 0 © M SPECIAL ENVIRONMENT 80960CF-30, -25, -16 32-BIT HIGH-PERFORMANCE SUPERSCALAR PROCESSOR • Socket and Object Code Compatible with 80960CA • Two Instructions/Clock Sustained Execution • Four 59 Mbytes/s DMA Channels with Data Chaining

Contextual Info: intei 80960CF-33, -25,-16 32-BIT HIGH PERFORMANCE SUPERSCALAR PROCESSOR • Socket and Object Code Compatible with 80960CA • Two Instructions/Clock Sustained Execution • Four 59 Mbytes/s DMA Channels with Data Chaining • Demultiplexed 32-bit Burst Bus with Pipelining

008 cow 734

Contextual Info: 80960CF-33, -25, -16 32-BIT HIGH PERFORMANCE SUPERSCALAR PROCESSOR • Socket and Object Code Compatible with 80960CA • Two Instructions/Clock Sustained Execution • Four 59 Mbytes/s DMA Channels with Data Chaining • Demultiplexed 3'2-bit Burst Bus with Pipelining

Contextual Info: in te i 0 M F [ i3 [m Y 0 N 80960CF-33, -25,-16 32-BIT HIGH PERFORMANCE SUPERSCALAR PROCESSOR • S o c k e t and O b jec t C o d e C o m p atib le w ith 8 0 96 0C A • T w o In s tru c tio n s /C lo c k S u stain ed E xecu tion • F ou r 59 M b y te s /s D M A C h an n els w ith D ata Chaining

Contextual Info: ADC12181 ADC12181 12-Bit, 10 MHz Self-Calibrating, Pipelined A/D Converter with Internal Sample & Hold Literature Number: SNAS040C ADC12181 12-Bit, 10 MHz Self-Calibrating, Pipelined A/D Converter with Internal Sample & Hold General Description The ADC12181 is a monolithic CMOS analog-to-digital converter capable of converting analog input signals into 12-bit