256OHR Search Results

PLCC256

Contextual Info: M W Y I U N U D A I 11 U « 1 1 H Y 6 7 1 8 1 1 0 /1 1 1 6 4 K X 1 8 B it S Y N C H R O N O U S C M O S S R A M PRELIMINARY DESCRIPTION This device integrates high-speed 64K x18 SRAM core, address registers, data input registers, a 2-bit burst address counter and Non-pipelined output. All synchronous inputs pass through registers controlled by a