HY6718110C Search Results

PLCC256

Contextual Info: M W Y I U N U D A I 11 U « 1 1 H Y 6 7 1 8 1 1 0 /1 1 1 6 4 K X 1 8 B it S Y N C H R O N O U S C M O S S R A M PRELIMINARY DESCRIPTION This device integrates high-speed 64K x18 SRAM core, address registers, data input registers, a 2-bit burst address counter and Non-pipelined output. All synchronous inputs pass through registers controlled by a

Contextual Info: HY6718110/111 HYUNDAI 64K X 18 Bit SYNCHRONOUS CMOS SRAM PRELIMINARY DESCRIPTION This device integrates high-speed 64K x18 SRAM core, address registers, data input registers, a 2-bit burst address counter and Non-pipelined output. All synchronous inputs pass through registers controlled by a

HY628400LLG

Abstract: HY628400LG-I HY628400LLP 8K*8 sram 52-PIN
Contextual Info: •HYU N DAI QUICK REFERENCE SRAM ORGANIZATION 64K bit 8Kx8 256K bit (32Kx8) 6 PART NUMBER SPEED(ns) FEATURES HY6264AP HY6264ALP HY6264ALLP HY6264AJ HY6264ALJ HY6264ALLJ 70/85/100/120 70/85/100/120 70/85/100/120 70/85/100/120 70/85/100/120 70/85/100/120