CY7C1350 Search Results

CY7C1350

Abstract: IDT71V546 MCM63Z736
Contextual Info: fax id: 1103 CY7C1350 PRELIMINARY 128Kx36 Pipelined SRAM with NoBL Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT devices IDT71V546, MT55L128L36P and MCM63Z736 • Supports 143-MHz bus operations with zero wait

CY7C1350

Contextual Info: fax id: 1103 * g S S M ^ % rrv rt n n n CY7C1350 PRELIMINARY 128Kx36 Pipelined SRAM with NoBL Architecture F e a tu re s F u n c t io n a l D e s c r ip t io n • Pin compatible and functionally e q u iv a le n ts ZBT™ devices IDT71V546, MT55L128L36P and MCM63Z736

CY7C1350B-80AC

Abstract: CY7C1350B
Contextual Info: PRELIMINARY CY7C1350B 128Kx36 Pipelined SRAM with NoBL Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT™ devices IDT71V546, MT55L128L36P, and MCM63Z736 • Supports 166-MHz bus operations with zero wait states

CY7C1350F

Abstract: CY7C1350F-250AC CY7C1350F-250AI CY7C1350F-250BGC
Contextual Info: CY7C1350F CY7C1350F 4-Mb 128K x 36 Pipelined SRAM with Nobl Architecture Functional Description[1] Features • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE

CY7C1350G

Contextual Info: CY7C1350G 4-Mbit 128K x 36 Pipelined SRAM with NoBL Architecture Functional Description[1] Features • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Byte Write capability

CY7C1350G

Contextual Info: CY7C1350G 4-Mbit 128 K x 36 Pipelined SRAM with NoBL Architecture 4-Mbit (128 K × 36) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT™ devices ■ Internally self-timed output buffer control to eliminate the need

CY7C1350F

Abstract: CY7C1350F-250AC CY7C1350F-250AI CY7C1350F-250BGC
Contextual Info: CY7C1350F CY7C1350F 4-Mb 128K x 36 Pipelined SRAM with Nobl Architecture Functional Description[1] Features • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE

CY7C1350

Contextual Info: fax id: 1103 CY7C1350 PRELIMINARY 128Kx36 Pipelined SRAM with NoBL Architecture Features Functional Description • Supports 143-MHz bus operations with zero wait states—Data is transferred on every clock The CY7C1350 is a 3.3V 128K by 36 synchronous-pipelined

CY7C1350

Abstract: IDT71V546 MCM63Z736
Contextual Info: fax id: 1103 Back CY7C1350 PRELIMINARY 128Kx36 Pipelined SRAM with NoBL Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT devices IDT71V546, MT55L128L36P and MCM63Z736 • Supports 143-MHz bus operations with zero wait

Contextual Info: 350A CY7C1350A/GVT71128ZC36 128Kx36 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between write and read cycles • Fast clock speed: 143, 133 and 100 MHzInternally synchronized registered outputs eliminate the need to control OE

CY7C1350

Abstract: CY7C1351 CY7C1353
Contextual Info: Cypress Semiconductor Qualification Report QTP# 98357 VERSION 1.1 May, 1999 4 Meg SRAM With NoBL Architecture R42D Technology, Hot Aluminum CY7C1350 128K x 36 Pipelined SRAM CY7C1351 128K x 36 Flow-Through SRAM CT7C1352 256K x 18 Pipelined SRAM CY7C1353

CY7C1350G

Contextual Info: CY7C1350G 4-Mbit 128 K x 36 Pipelined SRAM with NoBL Architecture 4-Mbit (128 K × 36) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT™ devices ■ Internally self-timed output buffer control to eliminate the need

CY7C1350B

Abstract: CY7C1329 CY7C1351B CY7C1352B CY7C1353B
Contextual Info: Cypress Semiconductor Product Qualification Report QTP# 99245 VERSION 3.0 December, 2000 4 Meg Synchronous SRAM R52D-3 Technology, Fab 4 CY7C1350B 128K x 36 Pipeline SRAM with NoBL Architecture CY7C1351B 128K x 36 Flow Through SRAM with NoBL™ Architecture

Contextual Info: CY7C1350G 4-Mbit 128 K x 36 Pipelined SRAM with NoBL Architecture 4-Mbit (128 K × 36) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT™ devices ■ Internally self-timed output buffer control to eliminate the need

CY7C1350B

Contextual Info: CY7C1350B PRELIMINARY CY7C1350B 128Kx36 Pipelined SRAM with NoBL Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT™ devices IDT71V546, MT55L128L36P, and MCM63Z736 • Supports 166-MHz bus operations with zero wait states

CY7C1350B

Abstract: 350B IDT71V546 MCM63Z736 DP330
Contextual Info: 350B PRELIMINARY CY7C1350B 128Kx36 Pipelined SRAM with NoBL Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT™ devices IDT71V546, MT55L128L36P, and MCM63Z736 • Supports 166-MHz bus operations with zero wait states

CY7C1350G

Contextual Info: CY7C1350G 4-Mbit 128K x 36 Pipelined SRAM with NoBL Architecture Functional Description[1] Features • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Byte Write capability

Contextual Info: CY7C1350G 4-Mbit 128 K x 36 Pipelined SRAM with NoBL Architecture 4-Mbit (128 K × 36) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT™ devices ■ Internally self-timed output buffer control to eliminate the need

CY7C1350F

Contextual Info: 350F PRELIMINARY CY7C1350F 128Kx36 Pipelined SRAM with NoBL Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Fully registered inputs and outputs for pipelined

Contextual Info: CY7C1350G 4-Mbit 128 K x 36 Pipelined SRAM with NoBL Architecture 4-Mbit (128 K × 36) Pipelined SRAM with NoBL™ Architecture Functional Description Features • Pin compatible and functionally equivalent to ZBT™ devices ■ Internally self-timed output buffer control to eliminate the need

CY7C1350G

Contextual Info: CY7C1350G 4-Mbit 128K x 36 Pipelined SRAM with NoBL Architecture Functional Description[1] Features • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Byte Write capability

Contextual Info: CY7C1350G 4-Mbit 128K x 36 Pipelined SRAM with NoBL Architecture Functional Description[1] Features • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Byte Write capability

A8299

Contextual Info: CY7C1350G 4-Mbit 128 K x 36 Pipelined SRAM with NoBL Architecture 4-Mbit (128 K × 36) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT™ devices ■ Internally self-timed output buffer control to eliminate the need

Contextual Info: CY7C1350G 4-Mbit 128K x 36 Pipelined SRAM with NoBL Architecture Functional Description[1] Features • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Byte Write capability