MULTIPRO Search Results

MARKING NO1A

Abstract: no3x ISL54230 ISL54230IIZ-T ISL54230IRTZ ISL54230IRTZ-T TB347 TB379 WLCSP chip attach
Contextual Info: ISL54230 Data Sheet May 28, 2009 FN6825.2 Octal Multiprotocol Switch Features The Intersil ISL54230 is a multiprotocol Quad Double-Pole Double-Throw DPDT analog switch that can operate from a single +2.0V to +5.5V supply. It contains eight SPDT (Single

STP2012

Abstract: SuperSPARC STP2016QFP
Contextual Info: STP2016 S un M ic r o e l e c t r o n ic s J u ly 1997 Clock-2 Generator DATA SHEET System Clock Generator D e s c r ip t io n The STP2016 Clock-2 Chip generates clock signals for components on the SBus and MBus. The MBus and SBus are used by SPARC processors, such as SuperSPARC™. The MBus is designed for multiprocessing MP , operating at

Contextual Info: SP503 Multiprotocol Transceiver • Single-Chip Serial Transceiver Supports Industry-Standard ■ Software-Selectable Protocols: — RS-232 V.28 — RS-422A (V.11, X.27) — RS-449 — RS-485 — V.35 — EIA-530 ■ Programmable Selection of Interface

JDSU oc-192 modulator

Abstract: JDS oc-192 modulator laser transmitter 1550 nm JDSU oc-192 jds xfp JDS Uniphase OC-192 STM-64 IR stm 64 laser diode 1550 nm Electroabsorption modulator Forward Path Laser Transmitter Module Diagram
Contextual Info: Communications modules & subsystemS Multiprotocol XFP Optical Transceiver—1550 nm for up to 40 km Reach JXP Series Key Benefits • Compliant with SONET OC-192 IR-2, 10 G Ethernet and 10 G Fibre Channel 10GBase-ER, and corresponding Forward Error Correction FEC rates from 9.95 Gbps to 11.35 Gbps

Contextual Info: 32K/64K X 9 CMOS PARALLEL IN-OUT FIFO MODULE FEATURES: First-In/First-Out memory module 64K x 9 IDT7M208 or 32K x 9 (IDT7M207) High speed: 20ns (max.) access time Asynchronous and sim ultaneous read and write Fully expandable: depth and/or width MASTER/SLAVE multiprocessing applications

82489DX AP-388

Abstract: 82489dx intel 82357 intel 82489dx
Contextual Info: 82489DX ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER 82489DX FEATURES OVERVIEW • Inter-Processor Interrupts ■ Advanced Interrupt Controller for 32-Bit Operating Systems ■ Various Addressing Schemes— Broadcast, Fixed, Lowest Priority, etc. ■ Solution for Multiprocessor Interrupt

SP510ECF-L

Abstract: sp510e
Contextual Info: SP510E ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER JULY 2012 REV. 1.0.0 GENERAL DESCRIPTION FEATURES The SP510E is a highly integrated physical layer solution that is configurable to support multiple serial standards. It incorporates eight drivers and eight

LTC1334

Abstract: EIA530 EIA530-A LTC2844 LTC2846 RS449 RS-530
Contextual Info: LTC2844 3.3V Software-Selectable Multiprotocol Transceiver U FEATURES • ■ ■ ■ ■ DESCRIPTIO The LTC 2844 is a 4-driver/4-receiver multiprotocol transceiver. The LTC2844 and LTC2846 form the core of a complete software-selectable DTE or DCE interface port that

RXD TXD DTR DSR RS232

Abstract: EIA530 EIA530-A LTC1344A LTC1543 LTC1544 LTC1546 RS449 107 6K tantalum capacitors 107 6k 109 capacitor
Contextual Info: Final Electrical Specifications LTC1546 Software-Selectable Multiprotocol Transceiver with Termination December 1999 U FEATURES • ■ ■ ■ ■ ■ ■ DESCRIPTIO The LTC 1546 is a 3-driver/3-receiver multiprotocol transceiver with on-chip cable termination. When combined with

cts 10mhz oscillator

Abstract: 0805R104K9BB 16 pin O/E/N relays db-26 connector pin assignment EIA-530A RS-449 SP3508
Contextual Info: PRELIMINARY SP3508 Rugged 3.3V, 20Mbps, 8 Channel Multiprotocol Transceiver with Programmable DCE/DTE and Termination Resistors FEATURES • Fast 20Mbps Differential Transmission Rates ■ Internal Transceiver Termination Resistors for V.11 & V.35 ■ Interface Modes:

75176

Abstract: rs449 pinout 1488 1489 standard rs232 pinout 75als180 75176 applications notes rs232 db25 pinout datasheet of 75176 rs423 pinout 75174
Contextual Info: Interface InfoCard 11 Multiprotocol Interface Solutions • ■ ■ ■ ■ Supports RS232, RS449, EIA530, EIA530-A, V.35, V.36, X.21 Protocols Single 5V Supply Integrated Switched Termination Flow-Through Pinout NET1, NET2 and TBR2 Compliant CHIPSET CLOCK AND

S6 67A

Abstract: galena motorola 401 siemens s5 IM 314 IM 304 7400 pin configuration k 4212 Minco Technology Labs motorola 68000 block diagram motorola 68000 watchdog SCR bt 107
Contextual Info: Microprocessors and Memory Technologies Group MC68LC302 Low Power Integrated Multiprotocol Processor Reference Manual Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding

TDA8007BHL/C2

Abstract: ISO7816 LQFP48 TDA8004 TDA8007B TDA8007BHL TDA8020
Contextual Info: TDA8007BHL Multiprotocol IC card interface Rev. 07 — 12 May 2010 Product data sheet 1. General description The TDA8007BHL/C4 is a cost-effective card interface for dual smart card readers. Controlled through a parallel bus, it meets all requirements of ISO 7816, GSM 11-11,

EIA530

Abstract: EIA530-A LTC1344A LTC1543 LTC1545 RS449
Contextual Info: LTC1545 Software-Selectable Multiprotocol Transceiver U FEATURES • ■ ■ ■ ■ ■ DESCRIPTIO The LTC 1545 is a 5-driver/5-receiver multiprotocol transceiver. The LTC1545 and LTC1543 form the core of a complete software-selectable DTE or DCE interface port that

API NETWORKS

Abstract: E9000 Marvell MIPS64 RM9200A
Contextual Info: RM9200A Released AM Integrated Multiprocessor DUAL E9000 CORES CACHE AND I/O COHERENCY PMC-Sierra’s RM9200A Integrated Processor is a high performance 64-bit MIPS-based dual-microprocessor with integrated memory and I/O interfaces. Each core provides: • 1 GHz operating frequency.

Contextual Info: SPEAr1310 Dual-core Cortex A9 embedded MPU for communications Data brief Features • CPU subsystem: – 2x ARM Cortex A9 cores, up to 600 MHz – Supporting both symmetric SMP and asymmetric (AMP) multiprocessing – 32+32 KB L1 Instructions/Data cache per

northbridge

Abstract: gigabyte 845 MOTHERBOARD CIRCUIT diagram INTEL 845 MOTHERBOARD CIRCUIT diagram AM2 athlon AMD 700 chipset AMD Athlon 64 AMD K6 AMD Athlon 64 X2 AMD Athlon 64 X2 thermal AMD Athlon X2
Contextual Info: Preliminary Information AMD Athlon MP TM Processor Model 6 OPGA Data Sheet for Multiprocesso ultiprocessor Platforms Publication # 25480 Rev: D Issue Date: June 2002 Preliminary Information 2001, 2002 Advanced Micro Devices, Inc. All rights reserved. The contents of this document are provided in connection with Advanced

XX11X

Abstract: 242690 Pentium Pro exfo 82453KX
Contextual Info: PENTIUM PRO PROCESSOR WITH 1 MB L2 CACHE AT 200 MHZ • Large integrated cache for multiprocessing systems ■ ■ ■ Binary compatible with applications running on previous members of the Intel microprocessor family Separate dedicated external system bus, and dedicated internal full-speed

Contextual Info: MC68302RC16 1/2 IL08 * ( VDD =+5V) C-MOS INTEGRATED MULTIPROTOCOL PROCESSOR -BOTTOM VIEW- N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 PIN NO. 1A 1B 1C 1D 1E 1F 1G 1H 1J 1K 1L 1M 1N 2A 2B 2C 2D 2E 2F 2G 2H 2J 2K 2L 2M 2N 3A 3B 3C 3D 3E

NII53001-7

Contextual Info: 12. Mailbox Core NII53001-7.1.0 Core Overview Multiprocessor environments can use the mailbox core with Avalon interface to send messages between processors. The mailbox core contains mutexes to ensure that only one processor modifies the mailbox contents at a time. The mailbox core must be used

CAN BUS

Abstract: ADSP-21160 virpt ADSP-21060
Contextual Info:  08/7,352& 66,1* Table 10-0. Figure 10-0. Listing 10-0. 2YHUYLHZ The ADSP-21160 includes functionality and features that allow the design of multiprocessing DSP systems. These features include distributed, on-chip arbitration for the shared external bus; a unified

verilog code parity

Abstract: 1 wire verilog code BUS BAR specification palasm tri state PAR64
Contextual Info: PCI Bus Applications April 1995, ver. 1 Introduction In Altera Devices Application Note 41 The peripheral component interconnect PCI bus is designed for multiprocessor systems and high-performance peripherals, including audio and video systems, network adapters, graphics accelerator boards,

interrupt in assembly for sharc

Abstract: ASDP-21065L
Contextual Info:  08/7,352& 66,1* Figure 7-0. Table 7-0. Listing 7-0. The processor includes functionality and features that enable users to design multiprocessing DSP systems. These features include • Distributed on-chip bus arbitration logic for bus mastership. This feature enables the processor to access external memory and the

SMD MARKING CODE A00b

Abstract: mil-std-1750a MARKING CODE A00B MIL-PRF-38510 as3 SMD Transistor MIL-STD-1750 ttl nim marking a00b SMD A009 pir chip
Contextual Info: Standard Products UT1750AR RadHard RISC Microprocessor Data Sheet May 2003 FEATURES q Operates in either RISC Reduced Instruction Set Computer mode or MIL-STD-1750A mode q Built-in multiprocessor bus arbitration and Direct Memory Access support (DMA) q Supports MIL-STD-1750A 32-bit floating-point