MPCL Search Results

VTXP-6

Abstract: TXC-06951 g803 Motorola 0X69 TXC-06951-MB 98822
Contextual Info: VTXP-6 Device STM-1/STS-3 SDH/SONET TU/VT Processor and Cross Connect TXC-06951 DATA SHEET PRELIMINARY TXC-06951-MB, Ed. 5 March 2006 FEATURES APPLICATIONS • Supports two line ports using the standard byte wide 19.44 MHz Telecom Bus, or a single line port using the standard byte wide 77.76 MHz Telecom Bus.

Contextual Info: PHAST -12N Device STM-4/OC-12 SDH/SONET Overhead Terminator with Telecom Bus Interface TXC-06312 DESCRIPTION • Bit-serial LVPECL SDH/SONET line interface with integrated clock recovery and clock synthesis - single 622.08 Mbit/s STM-4/OC-12 signal or - four 155.52 Mbit/s STM-1/OC-3 signals

ARM926T

Abstract: ic str 6454 s11 stopping compound motorola 7824 BT OSC26M CNC DRIVES ptc temperature sensor 400c 4*4 matrix keypad 17521 rca SAMSUNG NAND FLASH K9F5608
Contextual Info: i.MX21 Applications Processor Reference Manual Document Number: MC9328MX21RM Rev. 3 04/2007 How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370

Contextual Info: «HYUNDAI H Y 5 1 1 7 1 O O A S e r ie s 1 6 M x 1 - b it CM O S DRAM DESCRIPTION The HY5117100A is the new generation and fast dynamic RAM organized 16,777,216 x 1-bit. The HY5117100A utilizes Hyundai's CMOS silicon gate process technology as well as advanced circuit techniques to provide wide

ATI Radeon 9600

Abstract: 53c1030 RSB 8140 RADEOn Intel 82801EB MOTHERBOARD diagram ATI Radeon 7000 SE8500HW4 lm932 Intel 82801EB MOTHERBOARD layout IOP332
Contextual Info: Intel Server Board Set SE8500HW4 Technical Product Specification Intel order number D22893-001 Revision 1.0 May, 2005 Enterprise Platforms and Services – Marketing Revision History Intel® Server Board Set SE8500HW4 Revision History Date May 2005 Revision

car mp3 remote

Abstract: AT83SND2MP3 0011B 7524B AT83SND2CDVX AT83SND2CMP3 CRC16 FAT32 emmc pin mp3 player schematic diagram
Contextual Info: Features • MPEG I/II-Layer 3 Hardwired Decoder • • • • • • • • • • – Stand-alone MP3 Decoder – 48, 44.1, 32, 24, 22.05, 16 kHz Sampling Frequency – Separated Digital Volume Control on Left and Right Channels Software Control using 31 Steps

mmp 685 j

Abstract: rtl 8111 LC5734 LC5734H 2 pin crystal oscillator 20mhZ XL1 cf 455 e EN264 LC5797
Contextual Info: Ordering number : EN2642A CM OS LSI No. 2642A SANYO I i _LC5734, 5734H SINGLE-CHIP 4-BIT MICROCOMPUTER W ITH LCD DR IV E R S FOR LOW -VOLTAGE, LOW-OWER USE General Description The LC5734/5734H are single-chip 4-bit microcomputers w ith LCD drivers. The features of the LC5734/5734H include

MIP2F3

Abstract: MIP2F4 MIP382 MIP2E7DMY mip2f2 mip291 MIP414S MIP2E5DMY mip411 MIP3E3SMY equivalent
Contextual Info: 2009 ver.2 Semiconductor Selection Guide Microcomputers, Bipolar ICs, Discrete Semiconductors Caution for Safety „ This product contains Gallium Arsenide GaAs . DANGER GaAs powder and vapor are hazardous to human health if inhaled or ingested. Do not burn, destroy, cut, cleave off, or chemically dissolve the

Contextual Info: xr XRT86VL34 PRELIMINARY QUAD T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION OCTOBER 2005 REV. P1.0.7 GENERAL DESCRIPTION The XRT86VL34 is a four-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless,

user manual of XRT91L31

Contextual Info: XRT86SH328 SONET TO 28-T1/21-E1 PDH MAPPER - VOYAGER PIN AND ARCHITECTURE DESC MAY 2008 REV. 1.0.0 GENERAL DESCRIPTION The XRT86SH328 Voyager is a physical layer SONET/SDH to PDH mapper/demapper which enables T1/E1 aggregation to STS-3/STM-1 or STS1/ STM0 via standard VT1.5/VT2 or VC-11/VC-12 to

IDT3051

Abstract: hdlc 17X17 GR-253 GR-499-CORE XRT79L71 XRT79L71IB t59b
Contextual Info: PRELIMINARY XRT79L71 1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMER/LIU COMBO - HARDWARE OCTOBER 2010 GENERAL DESCRIPTION REV. P2.0.0 • Receiver Monitor mode handles up to 20 dB flat loss with 6 dB cable attenuation The XRT79L71 is a single channel, integrated DS3/

MA17

Abstract: MA18 MX98728EC Macronix marking GMAC
Contextual Info: MX98728EC 1.0 Features GMAC SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER FOR GENERIC APPLICATION • 1.6KB TX FIFO to support maximum network throughput in the full duplex mode • 16/8 bits SRAM interface of the packet buffer supporting burst DMA for on-chip FIFOs

SR52 W 18

Abstract: GR-253-CORE GR-499-CORE PR11 T7690 T7698 uig823
Contextual Info: a e re 8 AdLib OCR Evaluation systems Data Sheet September 2002 T7698 Quad T1/E1 Line Interface and Octal T1/E1 Monitor Features . Integrated quad T1/E1 line interface and octal T1/ El receive frame monitor with HDLC processor provides system QoS capabilities .

59013 h 331

Abstract: 59014 c 331 comcode 105 736 490 fcs 9013 GR-253-CORE JT-G704 JT-G706 TMXL28155 TR-62411 59014 c
Contextual Info: Preliminary Data Sheet, Rev 2 June, 2002 TMXL28155 SupermapperLite 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 1 Features • ■ Versatile IC supports 155/51 Mbits/s SONET/SDH interface solutions for T3, DS2, and T1/E1/J1 applications. Implementation supports both linear 1 + 1, unprotected and ring (UPSR) network topologies.

sk313

Abstract: BT 1840 PA cf 455 D403 A LC5734 LC5734H EVA-51 sanyo opu
Contextual Info: O rd erin g n u m b e r : E N 2642A CMOS LSI F SAKYO LC5734, 5734H No. 2642A SINGLE-CHIP 4-BIT MICROCOMPUTER W ITH LCD DR IV E R S FOR LOW -VOLTAGE, LOW-OWER USE i 7 7 " • '/ General Description , , The LC5734/5734H are single-chip 4-bit microcomputers w ith LCD drivers. The features of|pM&i.C573%/5734H include

motorola e1000

Abstract: transistor manual substitution FREE DOWNLOAD 8a21 gal programming timing chart Model CG 100 A STRIP TEMPLATE SC transistor manual substitution transistor substitution chart Transistor Substitution Data Book 1993 TMS320C80
Contextual Info: TMS320C80 MVP Code Generation Tools User’s Guide 1995 Microprocessor Development Systems Printed in U.S.A., March 1995 SDS SPRU108A TMS320C80 (MVP) Code Generation Tools 1995 User’s Guide TMS320C80 (MVP) Code Generation Tools User’s Guide Printed on Recycled Paper

7486 XOR GATE

Abstract: circuit diagram of half adder using IC 7486 7486 2-input xor gate ic 7486 XOR GATE pin configuration IC 7486 pin configuration of 7486 IC vhdl code for vending machine pin DIAGRAM OF IC 7486 data sheet IC 7408 laf 0001
Contextual Info: Lattice Semiconductor Handbook 1994 Click on one of the following choices: • Table of Contents • How to Use This Handbook • Go to Main Menu 1996 Lattice Semiconductor Corporation. All rights reserved. Lattice Semiconductor Handbook 1994 i Copyright © 1994 Lattice Semiconductor Corporation.

Contextual Info: IMISG509 REDUCED EMI CLOCK CHIP April 1996 CMOS LSI SPECTRUM SPREAD CLOCK GENERATOR P R O D U C T FEA TURES P R O D U C T D E S C R IP TIO N • Generates CPU clock signals for microprocessor systems ■ Reduces measured EMI by 10 dB nominal ■ 4V to 6V operating supply range

Contextual Info: IMISG501 SYSTEM CLOCK CHIP PATENT PENDING PRODUCT FEA TURES • Generates CPU Clock Signals for Microprocessor Systems ■ Reduces Measured EMI by 10 db nominal CMOS LSI REDUCED EMI CLOCK GENERATOR PRODUCT DESCRIPTION The IMISG501 is a spread spectrum clock

mip 0254

Abstract: Modified Booth Multipliers mp 1048 mp 1038 mip 836 EPC 1027 MP 1048 EM c80 Master Processor architecture mp 1026 parallel Multiplier Accumulator based on Radix-2
Contextual Info: TMS320C80 MVP Master Processor User’s Guide 1995 Digital Signal Processing Products Printed in U.S.A., March 1995 SPRU109A TMS320C80 (MVP) Master Processor 1995 User’s Guide TMS320C80 (MVP) Master Processor User’s Guide SPRU109A March 1995 Printed on Recycled Paper

i750

Abstract: TSK1V AU-AIS X0055 PCM30 XRT86SH221 XRT86SH221IB ASA17 intel i860
Contextual Info: XRT86SH221 PRELIMINARY SDH-TO-PDH FRAMER/MAPPER WITH INTEGRATED 21-CHANNEL E1 SH LIU MAY 2007 REV. P1.0.5 GENERAL DESCRIPTION The XRT86SH221 Voyager-Lite is a physical layer SDH to PDH mapper/demapper which enables E1 aggregation to STM-1 via standard VC-12 to AU-3

Contextual Info: SG521122124128 Spread Spectrum Clock Generator Preliminary FEATURES APPLICATIONS • • • • • • • • • • • • • • • • • • • • • Generates Spread Spectrum Clock SSC Programmable Frequencies from 10 to 120 MHz 1.25 and 3.25% Down-Spread Options

Contextual Info: IMISG502 SYSTEM CLOCK CHIP PATENT PENDING PRODUCT FEA TURES • Generates CPU Clock Signals for Microprocessor Systems ■ Reduces Measured EMI by 10 db nominal CMOS LSI SPREAD SPECTRUM CLOCK GENERATOR PRODUCT DESCRIPTION The IMISG502 is a spread spectrum clock

T7290A

Contextual Info: Data Sheet May 1998 T7688 5.0 V E1/CEPT Quad Line Interface Features • Four fully integrated E1 line interfaces ■ Includes all driver, receiver, equalization, clock recovery, and jitter attenuation functions ■ Ultralow power consumption ■ Robust operation for increased system margin