MC10EL3 Search Results

d22q

Abstract: MC12090D MC12090 MC10EL32 MC12083 MOTOROLA SEMICONDUCTOR MC10EL32 MOTOROLA SEMICONDUCTOR MC12090
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Not Recommended for New Designs MC12090 Consider MC12083 or MC10EL32 UHF Prescaler The MC12090 is a high–speed D master–slave flip–flop capable of toggle rates of over 700MHz. It was designed primarily for high–speed

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA ^4 Divider MC10EL33 MC100EL33 The MC10EL/100EL33 is an integrated +4 divider. The differential clock inputs and the V b b allow a differential, single-ended or AC coupled interface to the device. If used, the V b b output should be bypassed to ground with a

MC100EL32

Abstract: MC10EL32 AZ100EL32 AZ100EL32D AZ10EL32 AZ10EL32D
Contextual Info: DATA SHEET AZ10EL32 AZ100EL32 ARIZONA MICROTEK, INC. ÷2 Divider FEATURES • • • • • • 510ps Propagation Delay 3.0GHz Toggle Frequency High Bandwidth Output Transitions 75kΩ Internal Input Pulldown Resistors Direct Replacement for ON Semiconductor MC10EL32 & MC100EL32

100EL34G

Abstract: el34 MR 4010 MC100EL34 MC10EL34
Contextual Info: MC10EL34, MC100EL34 5V ECL ÷2, ÷4, ÷8 Clock Generation Chip Description The MC10/100EL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common

EL33

Abstract: HEL33 KEL33 MC100EL33 MC10EL33 kl-33
Contextual Info: MC10EL33, MC100EL33 5VĄECL ÷4 Divider The MC10EL/100EL33 is an integrated ÷4 divider. The differential clock inputs and the VBB allow a differential, single-ended or AC coupled interface to the device. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions,

kel33

Abstract: HEL33 kl-33 CIRCUIT DIAGRAM FOR IC 810 hl33
Contextual Info: MC10EL33, MC100EL33 5V ECL ÷4 Divider The MC10EL/100EL33 is an integrated ÷4 divider. The differential clock inputs and the VBB allow a differential, single-ended or AC coupled interface to the device. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions,

KEL31

Abstract: hel31 HEL31 SOIC8
Contextual Info: MC10EL31, MC100EL31 5 V ECL D Flip-Flop With Set and Reset The MC10EL/100EL31 is a D flip-flop with set and reset. The device is functionally equivalent to the E131 device with higher performance capabilities. With propagation delays and output transition times significantly faster than the E131, the EL31 is ideally

Contextual Info: MC10EL34, MC100EL34 5V ECL ÷2, ÷4, ÷8 Clock Generation Chip The MC10/100EL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common

mr 4020

Abstract: MC100EL35 HEL35 KL35 MC10EL35
Contextual Info: MC10EL35, MC100EL35 5VĄECL JK FlipĆFlop The MC10EL/100EL35 is a high speed JK flip-flop. The J/K data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The reset pin is asynchronous and is activated with a logic

diode 474 a

Abstract: MC68836 MC10EL32
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Not Recommended for New Designs MC12090 Consider MC12083 or MC10EL32 UHF Prescaler The MC12090 is a high-speed D master-slave flip-flop capable of toggle rates of over 700MHz. It was designed primarily for high-speed prescaling applications in communications and instrumentation. This

HEL33

Abstract: KEL33 EL33 MC100EL33 MC10EL33
Contextual Info: MC10EL33, MC100EL33 5V ECL ÷4 Divider Description Features • • Machine Model; > 100 V PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = −4.2 V to −5.7 V Internal Input Pulldown Resistors on CLK s and R.

MC100EL35

Contextual Info: MC10EL35, MC100EL35 5V ECL JK Flip-Flop Description The MC10EL/100EL35 is a high speed JK flip-flop. The J/K data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition

Contextual Info: MC10EL34, MC100EL34 5V ECL ÷2, ÷4, ÷8 Clock Generation Chip Description The MC10/100EL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common

HEL33

Abstract: MC10EL33 EL33 KEL33 MC100EL33 MC100EL33DG
Contextual Info: MC10EL33, MC100EL33 5V ECL ÷4 Divider Description Features • • Machine Model; > 100 V PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = −4.2 V to −5.7 V Internal Input Pulldown Resistors on CLK s and R.

KEL33

Abstract: kl-33 HEL33 MC100EL33 EL33 MC10EL33 KL33 hl33
Contextual Info: MC10EL33, MC100EL33 5V ECL ÷4 Divider The MC10EL/100EL33 is an integrated ÷4 divider. The differential clock inputs and the VBB allow a differential, single-ended or AC coupled interface to the device. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions,

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA D Flip-Flop With Set and Reset MC10EL31 MC100EL31 T h e M C 1 0 E U 1 0 0 E L 3 1 is a D flip-flop with set and reset. T h e device is functionally equ ivalent to the E131 capabilities. W ith propagation device with higher perform ance

MC100EL32

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA -s-2 Divider MC10EL32 MC100EL32 The MC10EL/100EL32 is an integrated +2 divider. The differential clock inputs and the V b b allow a differential, single-ended or AC coupled interface to the device. If used, the V b b output should be bypassed to

MC100EL35

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA JK Flip-Flop MC10EL35 MC100EL35 The MC10EL7100EL35 is a high speed JK flip-flop. The J/K data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of

MC100EL32

Abstract: KEL32
Contextual Info: MC10EL32, MC100EL32 5V ECL ÷2 Divider Description Features • 510 ps Propagation Delay • 3.0 GHz Toggle Frequency • ESD Protection: > 1 kV Human Body Model, • • • MARKING DIAGRAMS* 8 1 SOIC−8 D SUFFIX CASE 751 8 1 > 100 V Machine Model PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V

Contextual Info: MC10EL34, MC100EL34 5V ECL ÷2, ÷4, ÷8 Clock Generation Chip The MC10/100EL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA h-4 Divider MC10EL33 MC100EL33 The MC10EL/I00EL33 is an integrated +4 divider. The differential clock inputs and the V b b allow a differential, single-ended or AC coupled interface to the device. If used, the Vb b output should be bypassed to

Contextual Info: MC10EL31, MC100EL31 5 V ECL D Flip-Flop With Set and Reset The MC10EL/100EL31 is a D flip-flop with set and reset. The device is functionally equivalent to the E131 device with higher performance capabilities. With propagation delays and output transition times significantly faster than the E131, the EL31 is ideally

Contextual Info: MC10EL33, MC100EL33 5V ECL ÷4 Divider Description http://onsemi.com MARKING DIAGRAMS* 8 8 8 1 HEL33 ALYW G Features SOIC−8 D SUFFIX CASE 751 • • • • • • • • Machine Model; > 100 V PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V

KEL32

Abstract: HEL32 MC100EL32 KL32 MC10EL32
Contextual Info: MC10EL32, MC100EL32 5VĄECL ÷2 Divider The MC10EL/100EL32 is an integrated ÷2 divider. The differential clock inputs and the VBB allow a differential, single-ended or AC coupled interface to the device. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions,