525PS Search Results

K416

Contextual Info: 2.5V/3.3V/5V 1:4 PECL/ECL 2.5GHz CLOCK DRIVER WITH 2:1 DIFFERENTIAL INPUT MUX FEATURES DESCRIPTION • Guaranteed AC parameters over temp/voltage: • > 2.5GHz fMAX • < 25ps within-device skew • < 275ps tr/tf time • < 525ps prop delay ■ 2:1 Differential Mux input

Contextual Info: * SY10EL35 SY100EL35 JK FLIP-FLOP SYNERGY S E M IC O N D U C T O R DESCRIPTION FEATURES • 525ps propagation delay The S Y 10 /1 00EL35 are high-speed JK Flip-Flops. The J/K data enters the m aster portion of the flip -flop when the clock is LO W and is tran sfe rre d to the slave and,

Contextual Info: 0« SYNERGY SEMICONDUCTOR FEATURES DESCRIPTION • 525ps propagation delay The S Y 10/100EL35 are high-speed JK Flip-Flops. The J/K data enters the m aster portion of the flip -flo p when the clo ck is LO W and is tran sfe rre d to the slave and, thus, the outputs, upon a positive tran sitio n of the clock.

IC 745 GU

Contextual Info: £ S Y Ü E M IC C D E S C R IP T IO N FEATURES • 525ps propagation delay The SY 10/100EL35 are high-speed JK Flip-Flops. The J/K data enters the m aster portion of the flip -flop when the clock is LOW and is tran sfe rre d to the slave and, thus, the outputs, upon a positive tran sitio n of the clock.

SY100EL35

Abstract: SY100EL35ZC SY100EL35ZCTR SY10EL35 SY10EL35ZC SY10EL35ZCTR
Contextual Info: SY10EL35 SY100EL35 FINAL JK FLIP-FLOP FEATURES • ■ ■ ■ ■ DESCRIPTION 525ps propagation delay 2.2GHz toggle frequency High bandwidth output transistions Internal 75KΩ input pull-down resistors Available in 8-pin SOIC package The SY10/100EL35 are high-speed JK Flip-Flops. The

Contextual Info: * SY10EL35 SY100EL35 JK FLIP-FLOP SYNERGY SEMICONDUCTOR DESCRIPTION FEATURES • 525ps propagation delay The SY10/100EL35 are high-speed JK Flip-Flops. The J/K data enters the m aster portion of the flip-flop when the clock is LOW and is transferred to the slave and,

Contextual Info: 2.5V/3.3V/5V 1:5 LVPECL/PECL/ECL/HSTL Precision Edge SY100EP14U 2GHz CLOCK DRIVER WITH 2:1 FINAL DIFFERENTIAL INPUT MUX FEATURES • Guaranteed AC parameters over temp/voltage: • > 2GHz fMAX • < 25ps within-device skew • < 275ps tr/tf time • < 525ps prop delay

SY100EL35

Abstract: SY100EL35ZC SY100EL35ZCTR SY10EL35 SY10EL35ZC SY10EL35ZCTR 525PS 100EL35
Contextual Info: *SYNERGY SY10EL35 SY100EL35 JK FLIP-FLOP S E M IC O N D U C TO R FEATURES DESCRIPTION • 525ps propagation delay The S Y 10/100EL35 are high-speed JK Flip-Flops. The J/K data enters the m aster portion of the flip -flo p when the clo ck is LOW and Is transferred to the slave and,

Contextual Info: * SY10EL35 SY100EL35 JK FLIP-FLOP SYNERGY SEMICONDUCTOR DESCRIPTION FEATURES • 525ps propagation delay The SY10/100EL35 are high-speed JK Flip-Flops. The J/K data enters the m aster portion of the flip-flop when the clock is LOW and is transferred to the slave and,

HEL35

Abstract: MICREL marking
Contextual Info: SY10EL35 SY100EL35 FINAL JK FLIP-FLOP FEATURES • ■ ■ ■ ■ DESCRIPTION 525ps propagation delay 2.2GHz toggle frequency High bandwidth output transistions Internal 75KΩ input pull-down resistors Available in 8-pin SOIC package The SY10/100EL35 are high-speed JK Flip-Flops. The

Contextual Info: * SY10EL35 SY100EL35 JK FLIP-FLOP SYNERGY SEMICONDUCTOR DESCRIPTION FEATURES • 525ps propagation delay The SY10/100EL35 are high-speed JK Flip-Flops. The J/K data enters the m aster portion of the flip-flop when the clock is LOW and is transferred to the slave and,

Contextual Info: 2.5V/3.3V/5V 1:5 LVPECL/PECL/ECL/HSTL ClockWorks 2GHz CLOCK DRIVER WITH SY100EP14U 2:1 DIFFERENTIAL INPUT MUX FEATURES DESCRIPTION • Guaranteed AC parameters over temp/voltage: • > 2GHz fMAX • < 25ps within-device skew • < 275ps tr/tf time • < 525ps prop delay

Contextual Info: 2.5V/3.3V/5V 1:5 LVPECL/PECL/ECL/HSTL Precision Edge SY100EP14U 2GHz CLOCK DRIVER WITH 2:1 FINAL DIFFERENTIAL INPUT MUX FEATURES • Guaranteed AC parameters over temp/voltage: • > 2GHz fMAX • < 25ps within-device skew • < 275ps tr/tf time • < 525ps prop delay

HEL35

Abstract: SY100EL35 SY10EL35 SY10EL35LZC SY10EL35LZI SY10EL35LZITR
Contextual Info: Micrel, Inc. JK FLIP-FLOP FEATURES • ■ ■ ■ ■ SY10EL35 SY100EL35 SY10EL35 SY100EL35 DESCRIPTION 525ps propagation delay 2.2GHz toggle frequency High bandwidth output transistions Internal 75KΩ input pull-down resistors Available in 8-pin SOIC package

Contextual Info: *SYNERGY PRELIMINARY SY10EL35 SY100EL35 JK FLIP-FLOP SEMICONDUCTOR DESCRIPTION FEATURES 525ps propagation delay The SY10EL/100EL35 are high-speed JK Flip-Flops. The J/K data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave and, thus,

MC100EL35

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA JK Flip-Flop M C10EL35 M C100EL35 The M C10EL/100EL35 is a high speed JK flip-flop. The J/K data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock.

SMPTE 1080p level a

Contextual Info: 0XOWL GEN GF9330 High Performance SDTV/HDTV Deinterlacer PRELIMINARY DATA SHEET DEVICE OVERVIEW • De-interlace, Pass-Through and Film Frame Rate Down Conversion modes of operation The GF9330 is a high performance VDSP engine that performs high quality de-interlacing of interlaced digital

SY100EP14U

Abstract: SY100EP14UK4I SY100EP14UK4ITR XEP14U XEP14
Contextual Info: 2.5V/3.3V/5V 1:5 LVPECL/PECL/ECL/HSTL ClockWorks 2GHz CLOCK DRIVER WITH SY100EP14U 2:1 DIFFERENTIAL INPUT MUX FINAL FEATURES DESCRIPTION • Guaranteed AC parameters over temp/voltage: • > 2GHz fMAX • < 25ps within-device skew • < 275ps tr/tf time

VDS1120

Abstract: VDS2110 VDS5010 VDS3110 ECL10KH VDS1110 VDS2120 VDS5020 ECL10K 0-30ns
Contextual Info: Variable Delay Lines VDS Ultra High-Speed Variable Delay Lines The VDS family of high-speed vailable delay lines is available in a dual in-line package for a variety of types in either standard or custom specifications. FEATURES • High-speed SMD delay lines that have achieved 40 step

xep14u

Contextual Info: Precision Edge 2.5V/3.3V/5V 1:5 LVPECL/PECL/ECL/HSTL Precision Edge™ SY100EP14U SY100EP14U 2GHz CLOCK DRIVER WITH 2:1 FINAL DIFFERENTIAL INPUT MUX Micrel FEATURES • Guaranteed AC parameters over temp/voltage: • > 2GHz fMAX • < 25ps within-device skew

SY100EP14U

Abstract: SY100EP14UK4C SY100EP14UK4CTR SY100EP14UK4G SY100EP14UK4I SY100EP14UK4ITR XEP14U
Contextual Info: Micrel, Inc. 2.5V/3.3V/5V 1:5 LVPECL/PECL/ ECL/HSTL 2GHz CLOCK DRIVER WITH 2:1 DIFFERENTIAL INPUT MUX Precision Edge SY100EP14U Precision Edge® SY100EP14U FEATURES • • • • • • • • • Guaranteed AC parameters over temp/voltage: • > 2GHz fMAX

smpte 274m

Abstract: 4.1 home theatre diagram 1080p field pattern GF9330 SMPTE 267M 5501 7 segment circuit diagram of video wall deinterlacer film mode detection diagram of video wall home theater circuit diagram 7.2 Channels, 100 W
Contextual Info: GF9330 High Performance HDTV/SDTV Deinterlacer GF9330 Data Sheet Features Device Overview • • • • • The GF9330 is a 10-bit high performance VDSP engine that performs high quality motion adaptive de-interlacing of interlaced digital video signals. The GF9330 supports

MC100EL35

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA JK Flip-Flop MC10EL35 MC100EL35 The MC10EL7100EL35 is a high speed JK flip-flop. The J/K data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of

GF9330

Abstract: GF9330-CBP GF9331 GS9021 ieee format for w16 engine SMPTE 296M smpte 274m image enhancer
Contextual Info: 0XOWL GEN GF9330 High Performance SDTV/HDTV Deinterlacer PRELIMINARY DATA SHEET DEVICE OVERVIEW • De-interlace, Pass-Through and Film Frame Rate Down Conversion modes of operation The GF9330 is a high performance VDSP engine that performs high quality de-interlacing of interlaced digital