MARKING TRF Search Results

W55H

Abstract: SFSCE10M7WF05 NE604N SMD marking code 55B w55c w55g w55e 3542C W55D R CFXCA450
Contextual Info: 通信设备用滤波器 05.01.28 中频用 陶瓷滤波器 CERAFILr (kHz, MHz) o kHz SMD型 CFXC_系列 6.5±0.3 (6) (5) (4) 5.2 3.8 EIAJ CODE * (1) (2) (3) Input terminal marking Input terminal marking (5.5) 0.4 1.4 1.9 (3.5) (4.925) 0.5 (5.8) (6) (5) (4)

NT6SM32M16AG-S1

Abstract: NT6SM16M32 128M32 NT6SM16M32AK NT6SM32M16AG Lpddr2 Idd1 8M32R NT6SM16M32AK-S1 lpddr2 layout lpddr2 256mb
Contextual Info: 512Mb LPSDR SDRAM NT6SM32M16AG / NT6SM16M32AK / NT6SM16M32RAK Feature  Options Fully synchronous; all signals registered on positive edge of  Marking VDD /VDDQ system clock -1.8V/1.8V  M Internal, pipelined operation; column address can be changed

Lpddr2 Idd7

Abstract: COMMAND42 lpddr2 256mb lpddr2 layout NT6SM32M16AG-S2 LPDDR2 1Gb Memory NT6SM16M32
Contextual Info: 512Mb LPSDR SDRAM NT6SM32M16AG / NT6SM16M32AK / NT6SM16M32RAK Feature  Options Fully synchronous; all signals registered on positive edge of Marking  VDD /VDDQ system clock -1.8V/1.8V  M Internal, pipelined operation; column address can be changed

Lpddr2 Idd7

Abstract: 216-ball LPDDR2 NT6SM16M32 NT6SM16M32AK-S1
Contextual Info: 512Mb LPSDR SDRAM NT6SM16M32AK Feature  Options Fully synchronous; all signals registered on positive edge of Marking  VDD /VDDQ system clock -1.8V/1.8V  M Internal, pipelined operation; column address can be changed  Configuration every clock cycle

Lpddr2 Idd7

Abstract: Jedec lpddr2 216-ball LPDDR 8Gb lpddr2-s2
Contextual Info: 256Mb LPSDR SDRAM NT6SM8M32AK Feature  Options Fully synchronous; all signals registered on positive edge of Marking  VDD /VDDQ system clock -1.8V/1.8V  M Internal, pipelined operation; column address can be changed  Configuration every clock cycle

NTC 200-9

Abstract: a2240 128M16 A1930 NT6SM16M32
Contextual Info: 512Mb LPSDR SDRAM NT6SM16M32AK Feature  Options Fully synchronous; all signals registered on positive edge of Marking  VDD /VDDQ system clock -1.8V/1.8V  M Internal, pipelined operation; column address can be changed  Configuration every clock cycle

lpddr2 256mb

Abstract: NT6DM8M32AC-T1 NT6DM16M16AD NT6DM8M32AC lpddr2 layout NT6DM8M32 Dual LPDDR2 lpddr2 256mb kgd lpddr2-s2
Contextual Info: 256Mb LPDDR SDRAM NT6DM16M16AD / NT6DM8M32AC Options Feature  Double-data rate architecture; two data transfer per clock cycle  Bidirectional, data strobe DQS is transmitted/received with data, to be used in capturing data at the receiver Marking  VDD /VDDQ

A1930

Contextual Info: 256Mb LPSDR SDRAM NT6SM8M32AK Feature  Options Fully synchronous; all signals registered on positive edge of Marking  VDD /VDDQ system clock -1.8V/1.8V  M Internal, pipelined operation; column address can be changed  Configuration every clock cycle

NT6SM16M16AG-S1

Abstract: lpddr2-s2 NT6SM16M16AG NT6SM16M16AG-S1I 128T64
Contextual Info: 256Mb LPSDR SDRAM NT6SM16M16AG NT6SM8M32AK Feature Options Fully synchronous; all signals registered on positive edge of z z Marking VDD /VDDQ system clock -1.8V/1.8V M Internal, pipelined operation; column address can be changed z z every clock cycle

Contextual Info: Data Sheet Rev.1.1 17.11.2010 4096MB DDR3 – SDRAM RDIMM 240 Pin registered DIMM Features: • SGP04G72D1BD2MT-CCRT 4096MB PC3-10600 in FBGA Technology RoHS compliant Options: • Data Rate / Latency DDR3 1333 MT/s CL9 DDR3 1066 MT/s CL7 Marking -CC -BB 

Contextual Info: Data Sheet Rev.1.1 17.11.2010 4096MB DDR3 – SDRAM RDIMM 240 Pin registered DIMM Features: • SGP04G72D1BD2MT-CCRT 4096MB PC3-10600 in FBGA Technology RoHS compliant Options: • Data Rate / Latency DDR3 1333 MT/s CL9 DDR3 1066 MT/s CL7 Marking -CC -BB 

NT6DM16M

Contextual Info: 512Mb LPDDR SDRAM NT6DM32M16AD / NT6DM16M32AC Feature Options  Double-data rate architecture; two data transfer per clock cycle  Bidirectional, data strobe DQS is transmitted/received with Marking  VDD /VDDQ -1.8V/1.8V M data, to be used in capturing data at the receiver

NT6DM32M16AD-T1

Abstract: NT6DM32M16AD NT6DM16M32AC-T1 NT6DM16M32AC NT6DM16M32AC-T3 216-ball NT6DM32M16AD-T3 256M16 lpddr2 256mb lpddr2 layout
Contextual Info: 512Mb LPDDR SDRAM NT6DM32M16AD / NT6DM16M32AC Feature Options  Double-data rate architecture; two data transfer per clock cycle  Bidirectional, data strobe DQS is transmitted/received with Marking  VDD /VDDQ -1.8V/1.8V M data, to be used in capturing data at the receiver

LPDDR 8Gb

Abstract: lpddr2 256mb NT6DM32M16AD-T1 NT6DM32M16AD nanya lpddr2 spec
Contextual Info: 512Mb LPDDR SDRAM NT6DM32M16AD / NT6DM16M32AC Feature Options  Double-data rate architecture; two data transfer per clock cycle  Bidirectional, data strobe DQS is transmitted/received with Marking  VDD /VDDQ -1.8V/1.8V M data, to be used in capturing data at the receiver

Contextual Info: Data Sheet Rev.1.0 14.01.2011 1024MB DDR3 – SDRAM UDIMM 240 Pin UDIMM Features: SGU01G64A1BG1SA-xxR • 1GByte in FBGA Technology •      RoHS compliant Options:   Data Rate / Latency DDR3 1066 MT/s CL7 DDR3 1333 MT/s CL9 Marking -BB

Contextual Info: Data Sheet Rev.1.0 25.02.2011 4096MB DDR3 – SDRAM DIMM 240 Pin UDIMM Features: SGU04G64B1BD2MT-xxR • 4GByte in FBGA Technology •      RoHS compliant Options:    Data Rate / Latency DDR3 1066 MT/s CL7 DDR3 1333 MT/s CL9 Marking

Contextual Info: Data Sheet Rev.1.1 24.05.2011 2048MB DDR3 – SDRAM UDIMM 240 Pin UDIMM Features: SGU02G64A1BD1MT-xxR • 2GByte in FBGA Technology RoHS compliant Options: • Data Rate / Latency DDR3 1066 MT/s CL7 DDR3 1333 MT/s CL9 Marking -BB -CC      

Contextual Info: Preliminary‡ 512Mb: x16, x32 Automotive Mobile LPSDR SDRAM Features Automotive Mobile LPSDR SDRAM MT48H32M16LF – 8 Meg x 16 x 4 Banks MT48H16M32LF/LG – 4 Meg x 32 x 4 Banks Features Options Marking • VDD/VDDQ: 1.8V/1.8V • Addressing – Standard addressing option

Contextual Info: Data Sheet Rev.1.0 25.02.2011 4096MB DDR3 – SDRAM DIMM 240 Pin UDIMM Features: SGU04G64B1BD2MT-xxR • 4GByte in FBGA Technology •      RoHS compliant Options:    Data Rate / Latency DDR3 1066 MT/s CL7 DDR3 1333 MT/s CL9 Marking

Contextual Info: Data Sheet Rev.1.1 24.05.2011 2048MB DDR3 – SDRAM UDIMM 240 Pin UDIMM Features: SGU02G64A1BD1MT-xxR • 2GByte in FBGA Technology RoHS compliant Options: • Data Rate / Latency DDR3 1066 MT/s CL7 DDR3 1333 MT/s CL9 Marking -BB -CC      

B63URCB

Contextual Info: Data Sheet Rev.1.0 04.02.2011 2048MB DDR3 – SDRAM DIMM 240 Pin UDIMM Features: SGU02G64B1BG2SA-xxR • 2GByte in FBGA Technology •      RoHS compliant Options:  Data Rate / Latency DDR3 1066 MT/s CL7 DDR3 1333 MT/s CL9 Marking -BB -CC

Contextual Info: Data Sheet Rev.1.0 20.11.2010 1GB DDR2 – SDRAM registered DIMM Features: • 240 Pin RDIMM SEP01G72J2BF1SA-30R 1GB PC2-5300 in FBGA Technology RoHS compliant •      Options:  Data Rate / Latency DDR2 533MT/s CL4 DDR2 667MT/s CL5  Marking

MT48LCM32B2

Abstract: MT48LC2M3B2b5 MT48LCM32B2P MT48LCM32 Micron Technology automotive
Contextual Info: Preliminary‡ 64Mb: x32 Automotive SDRAM Features Automotive SDR SDRAM MT48LC2M32B2 – 512K x 32 x 4 Banks Features Options Marking • Configuration – 2 Meg x 32 512K x 32 x 4 banks • Plastic package – OCPL on page – 86-pin TSOP II (400 mil) standard

Contextual Info: Data Sheet Rev.1.0 12.12.2012 2048MB DDR3 – SDRAM registered ECC VLP Mini-RDIMM 244 Pin ECC Mini-RDIMM Features: SGH02G72C1BD1MT-XX W RT • •     RoHS compliant Options:  Data Rate / Latency DDR3 1066 MT/s CL7 DDR3 1333 MT/s CL9 Marking