LVELT22 Search Results

E142 wafer format

Abstract: HEL32 MR 4710 IC 300w power amplifier circuit diagram HEL05 klt22 HEL12 HEL31 HEL16 HLT22 HLT28
Contextual Info: DL140/D Rev. 6, Jan-2001 High Performance ECL Data ECLinPS and ECLinPS Lite™ High Performance ECL Device Data ECLinPS, ECLinPS Lite, and Low Voltage ECLinPS DL140/D Rev. 6, Jan–2001  SCILLC, 2001 Previous Edition  2000 “All Rights Reserved”

KVT22

Abstract: KR22 MC100LVELT22
Contextual Info: LVELT22 3.3V Dual LVTTL/LVCMOS to Differential LVPECL Translator Description The LVELT22 is a dual LVTTL/LVCMOS to differential LVPECL translator. Because LVPECL Low Voltage Positive ECL levels are used, only +3.3 V and ground are required. The small outline

KVT22

Abstract: KR22 MC100LVELT22 MC100LVELT22D MC100LVELT22DR2
Contextual Info: LVELT22 3.3VĄDual LVTTL/LVCMOS to Differential LVPECL Translator The LVELT22 is a dual LVTTL/LVCMOS to differential LVPECL translator. Because LVPECL Low Voltage Positive ECL levels are used, only +3.3 V and ground are required. The small outline

Contextual Info: LVELT22 3.3V Dual LVTTL/LVCMOS to Differential LVPECL Translator Description Features • • • • • • • 350 ps Typical Propagation Delay <100 ps Output−to−Output Skew Flow Through Pinouts The 100 Series Contains Temperature Compensation

DL140

Abstract: MC100LVELT22
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Dual LVTTL/LVCMOS to LVELT22 Differential LVPECL Translator The LVELT22 is a dual LVTTL/LVCMOS to differential LVPECL translator. Because LVPECL Low Voltage Positive ECL levels are used, only +3.3V and ground are required. The small outline 8-lead SOIC

el90

Abstract: H352 DL122 DL140 ept20 EPT25 LVEL92 EPT22 H124 ttl databook
Contextual Info: AN1672/D The ECL Translator Guide ECL • TTL • PECL • LVECL • LVPECL • CMOS • LVTTL How To Make Them Talk To Each Other http://onsemi.com Prepared by: Paul Shockman, Paul Hunt ON Semiconductor Logic Applications Engineering APPLICATION NOTE Translation between ECL signals off different power

KR22

Contextual Info: LVELT22 3.3V Dual LVTTL/LVCMOS to Differential LVPECL Translator Description Features • • • • • • • 350 ps Typical Propagation Delay <100 ps Output−to−Output Skew Flow Through Pinouts The 100 Series Contains Temperature Compensation

Contextual Info: LVELT22 3.3V Dual LVTTL/LVCMOS to Differential LVPECL Translator Description The LVELT22 is a dual LVTTL/LVCMOS to differential LVPECL translator. Because LVPECL Low Voltage Positive ECL levels are used, only +3.3 V and ground are required. The small outline

KVT22

Abstract: KR22 MC100LVELT22 948R
Contextual Info: LVELT22 3.3V Dual LVTTL/LVCMOS to Differential LVPECL Translator Description The LVELT22 is a dual LVTTL/LVCMOS to differential LVPECL translator. Because LVPECL Low Voltage Positive ECL levels are used, only +3.3 V and ground are required. The small outline

H124

Abstract: LVEL17 MC10EPT20
Contextual Info: AN1672/D The ECL Translator Guide PECL • LVPECL • NECL • TTL • LVTTL/LVCMOS • CMOS Prepared by: Paul Shockman ON Semiconductor Logic Applications Engineering APPLICATION NOTE Objective This application note is intended to provide the basic device selection and connection information to enable signal

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Dual LVTTL/LVCMOS to D ifferential LVPECL Translator LVELT22 The LVELT22 is a dual LVTTL/LVCMOS to differential LVPECL translator. Because LVPECL Low Voltage Positive ECL levels are used, only +3.3V and ground are required. The small outline 8-lead SOIC

MC10EPT25

Abstract: MC10EPT22 MC10EPT24 MC10EPT23 MC10EPT21 ttl 7709 AND8072 HCT CMOS family characteristics AN1568 AND8020
Contextual Info: AN1672/D The ECL Translator Guide PECL • LVPECL • NECL • TTL • LVTTL/LVCMOS • CMOS http://onsemi.com Prepared by: Paul Shockman ON Semiconductor APPLICATION NOTE Objective receiver in the LOW state. In contrast, ECL drivers source current in both HIGH and LOW states to the receiver).

AND8090

Abstract: kvt22 KR22 MC100LVELT22 MC100LVELT22D MC100LVELT22DR2 MC100LVELT22DT MC100LVELT22DTR2
Contextual Info: LVELT22 3.3V Dual LVTTL/LVCMOS to Differential LVPECL Translator The LVELT22 is a dual LVTTL/LVCMOS to differential LVPECL translator. Because LVPECL Low Voltage Positive ECL levels are used, only +3.3 V and ground are required. The small outline

kvt22

Abstract: BD 140 transistor KR22 MC100LVELT22
Contextual Info: LVELT22 3.3V Dual LVTTL/LVCMOS to Differential LVPECL Translator Description The LVELT22 is a dual LVTTL/LVCMOS to differential LVPECL translator. Because LVPECL Low Voltage Positive ECL levels are used, only +3.3 V and ground are required. The small outline

KVT22

Abstract: marking code E2 logic gate EP MARKING CODE SOIC 8 DFN8 KR22 MC100LVELT22
Contextual Info: LVELT22 3.3V Dual LVTTL/LVCMOS to Differential LVPECL Translator Description Features • • • • • • • 350 ps Typical Propagation Delay <100 ps Output−to−Output Skew Flow Through Pinouts The 100 Series Contains Temperature Compensation

SPICE model for UC3844

Abstract: UC3843 spice model tl494 spice model EB407 Basic Halogen Converter MTP2N10 180V - 240V igbt dimmer UC3845 pspice model mosfet cross reference spice model moc3061 uc3843 flyback supply opto-coupler
Contextual Info: BR1522/D Rev. 2, Aug-2000 Technical Literature Selector Guide and Cross Reference ON Semiconductor A Listing and Cross Reference of Available Technical Literature from ON Semiconductor ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC SCILLC . SCILLC reserves the right to make changes without further

k0304

Abstract: K0204 N03m DIODE C06 15 k0203 26M transistor 473e K0607WB resistor 56E L05 diode
Contextual Info: AND8010/D ECLinPS Lite LVELT22 SPICE Model Kit Prepared by Paul Shockman http://onsemi.com APPLICATION NOTE ON Semiconductor Logic Applications Engineering Introduction The objective of this kit is to provide schematic and SPICE parameter information for performing system level

EL90

Abstract: AN1568 AND8020 AND8066 AND8072 MC10EP195 H124 MC10EPT22 MC10EPT20
Contextual Info: AN1672/D The ECL Translator Guide PECL • LVPECL • NECL • TTL • LVTTL/LVCMOS • CMOS http://onsemi.com Prepared by: Paul Shockman ON Semiconductor APPLICATION NOTE Objective This application note is intended to provide the basic device selection and connection information to enable signal

ELT24

Abstract: AN1568 AND8020 AND8066 AND8072 MC10EP195 H124 MC10EPT22 MC10EPT20
Contextual Info: AN1672/D The ECL Translator Guide PECL • LVPECL • NECL • TTL • LVTTL/LVCMOS • CMOS http://onsemi.com Prepared by: Paul Shockman ON Semiconductor APPLICATION NOTE Objective This application note is intended to provide the basic device selection and connection information to enable signal

N03m

Abstract: 794e k0203 N04m MC100LVELT22 motorola LOGIC L05 diode k0305 NE 544 spice model
Contextual Info: AND8010/D  ECLinPS Lite LVELT22 SPICE Model Kit Prepared by Paul Shockman http://onsemi.com APPLICATION NOTE Motorola Logic Applications Engineering Introduction The objective of this kit is to provide schematic and SPICE parameter information for performing system level

kvt22

Abstract: KR22 MC100LVELT22
Contextual Info: LVELT22 3.3V Dual LVTTL/LVCMOS to Differential LVPECL Translator Description The LVELT22 is a dual LVTTL/LVCMOS to differential LVPECL translator. Because LVPECL Low Voltage Positive ECL levels are used, only +3.3 V and ground are required. The small outline