LBST Search Results

LBST100

Abstract: LBST125 bo75
Contextual Info: 198 4/3/01 N/A LAS N/A N/A INIT I A L -RELEASE 15mm NOTES : 1. MATERIAL COMPOSITION: LBST - THERMOSET 2. DIMENSIONS ARE m m / [ INCHES], 3. TOLERANCES ARE ±.01 UNLESS OTHERWISE SPECIFIED. P/N AMPERE RATING CONN TYPE RMS SYM RATING TOROUE LBS-IN LB5TB0 LB5T80

Contextual Info: Major League Electronics .100 cl Board Stacker Socket Strip - using .025" sq. pins C L Ordering Information BSSQ-1 XX - D - XX - XX - XX - XXX - LF Pins Per Row 01 - 40 Lead Free Row Specification D = Dual Row Polarized Position Leave blank if not needed If required, specify empty pin position, e.g. 012 for Pin 12

Contextual Info: V58C2128 804/404/164 SB HIGH PERFORMANCE 128 Mbit DDR SDRAM 4 BANKS X 4Mbit X 8 (804) 4 BANKS X 2Mbit X 16 (164) 4 BANKS X 8Mbit X 4 (404) 5 6 DDR400 DDR333 7.5 ns 7.5 ns Clock Cycle Time (tCK2.5) 6ns 6 ns Clock Cycle Time (tCK3) 5ns 6 ns 200 MHz 166 MHz Clock Cycle Time (tCK2)

Contextual Info: Freescale Semiconductor Advance Information Document number: MC34708 Rev. 10.0, 2/2013 Power Management Integrated Circuit PMIC for i.MX50/53 Families 34708 The MC34708 is the Power Management Integrated Circuit (PMIC) designed specifically for use with the Freescale i.MX50 and i.MX53

Contextual Info: UCC28180 www.ti.com SLUSBQ5A – NOVEMBER 2013 – REVISED NOVEMBER 2013 Programmable Frequency, Continuous Conduction Mode CCM , Boost Power Factor Correction (PFC) Controller Check for Samples: UCC28180 FEATURES DESCRIPTION • • The UCC28180 is a flexible and easy-to-use, 8-pin,

atx pfc Schematic System General

Abstract: U100k
Contextual Info: UCC28019A www.ti.com. SLUS828B – DECEMBER 2008 – REVISED APRIL 2009 8-Pin Continuous Conduction Mode CCM PFC Controller

NVR 1550

Abstract: ATO-4 MC13892C MC33xx MC13892D rechargeable coin battery MC13892J krt30 MC13892DJVL MC13892B
Contextual Info: Freescale Semiconductor Document Number: MC13892 Rev. 18.0, 10/2012 Power Management Integrated Circuit PMIC for i.MX35/51 13892 The MC13892 is a Power Management Integrated Circuit (PMIC) designed specifically for use with the Freescale i.MX35 and i.MX51

Contextual Info: in tj 2-MBIT 128K x 16, 256K x 8 BOOT BLOCK FLASH MEMORY FAMILY 28F200BX-T/B, 28F002BX-T/B • x8/x16 Input/Output Architecture — 28F200BX-T, 28F200BX-B — For High Performance and High Integration 16-bit and 32-bit CPUs ■ x8-only Input/Output Architecture

A23 1101 01A

Abstract: E1-PCM-30 Bt8370KPF RJ48C EE - 19c TRANSFORMER E1-PCM-30 ch chips 65554 RDL2 MC68302 TR-303
Contextual Info: Bt8370/75/76 Fully Integrated T1/E1 Framer and Line Interface The Bt8370/75/76 is a family of single-chip transceivers for T1/E1 and Integrated Distinguishing Features Service Digital Network ISDN primary rate interfaces, operating at 1.544 Mbps or 2.048 Mbps. These devices combine a sophisticated framer, transmit and receive slip ! Single-chip T1/E1 framer with short/long

Contextual Info: HI-6130 / HI-6131 / HI-6132 MIL-STD-1553 / MIL-STD-1760 3.3V BC / MT / RT Multi-Terminal Device GENERAL DESCPIPTION • The 3.3V CMOS HI-613x device provides a complete single- or multi-function interface between a host processor and MIL-STD-1553B bus. Each IC contains

MC13892VL

Abstract: M13892 MC13892 PC13892VL i.mx51 FC135 MC13892 registers MICRO CRYSTAL CC7V-T1A 32,768Khz VLS252012 MC13892VK
Contextual Info: Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages.

Contextual Info: Major League Electronics .100 cl Board Stacker Socket Strips - Custom using .025" sq. pins C L Ordering Information BSSQC-1 XX - D - XXX - XX - XX - XXX - XX - XXX - LF Pins Per Row 01 - 40 Lead Free Row Specification D = Dual Row Polarized Position Leave blank if not needed

K4H560838C-TCB3

Abstract: DDR200 DDR266A DDR266B DDR333 k4h560838ctcb3
Contextual Info: 256Mb C-die x4/8 DDR SDRAM DDR SDRAM Specification Version 0.7 - 1 - REV. 0.7 Jan. 31. 2002 256Mb C-die(x4/8) DDR SDRAM Revision History Version 0 (May, 2001) - First version for internal review of 256Mb C-die. Version 0.1 (July, 2001) - Updated target current spec(TSOP package base)

Contextual Info: ESMT M13S128168A Operation temperature condition -40°C~85°C Revision History Revision 1.0 03 Jan. 2007 - Original Revision 1.1 (19 Mar. 2008) - Add BGA package - Modify the waveform of Power up & Initialization Sequence - Modify the θ value of TSOPII package dimension

Contextual Info: ESMT M13S2561616A Revision History Revision 0.1 28 Apr. 2006 - Original Revision 1.0 (07 Jun. 2006) - Delete Preliminary at ever page - Revise typing error of page1 Revision 1.1 (09 May. 2007) - Modify PD, DC specifications and MRS Revision 1.2 (12 Jun. 2007)

Contextual Info: ESMT M13S64164A Revision History Revision 0.1 23 Oct. 2006 - Original Revision 0.2 (06 Jun. 2007) - Add BGA type spec Revision 0.3 (20 Jul. 2007) - Modify BGA assignment Revision 0.4 (01 Oct. 2007) - Modify IDD spec. Revision 1.0 (20 Nov. 2007) - Delete “Preliminary”

Contextual Info: ESMT M53D128168A 2E Operation Temperature Condition -40°C~85°C Mobile DDR SDRAM 2M x16 Bit x 4 Banks Mobile DDR SDRAM Features z z z z z z z z z z JEDEC Standard Internal pipelined double-data-rate architecture, two data access per clock cycle Bi-directional data strobe (DQS)

Contextual Info: R&E International RE46C105 Piezoelectric Horn Driver with Voltage Regulator and LED Driver Circuit Preliminary Specification General Description Features The RE46C105 is a piezoelectric horn driver with a voltage regulator and an open drain NMOS driver suitable for use with a light

supi 3 ls

Contextual Info: AUTOMATION User manual IBS SUPI 3 OPC UM E Order No.: — INTERBUS IBS SUPI 3 OPC protocol chip AUTOMATION User manual IBS SUPI 3 OPC INTERBUS protocol chip 04/2009 Designation: IBS SUPI 3 OPC UM E Revision: 05 Order No.: — This user manual is valid for:

Contextual Info: V58C2512 804/404/164 SD HIGH PERFORMANCE 512 Mbit DDR SDRAM 4 BANKS X 16Mbit X 8 (804) 4 BANKS X 32Mbit X 4 (404) 4 BANKS X 8Mbit X 16 (164) 4 5 6 75 DDR500 DDR400 DDR333 DDR266 - 6ns 6ns 7.5ns 4ns 5ns - - 250 MHz 200 MHz 166 MHz 133 MHz Clock Cycle Time (tCK2.5)

Contextual Info: V58C2256 804/404/164 SA HIGH PERFORMANCE 256 Mbit DDR SDRAM 4 BANKS X 8Mbit X 8 (804) 4 BANKS X 4Mbit X 16 (164) 4 BANKS X 16Mbit X 4 (404) 5B 5 6 7 DDR400 DDR400 DDR333 DDR266 7.5 ns 7.5 ns 7.5 ns 7.5ns Clock Cycle Time (tCK2.5) 5ns 6ns 6 ns 7ns Clock Cycle Time (tCK3)

Contextual Info: V58C2128 804/404/164 SB HIGH PERFORMANCE 128 Mbit DDR SDRAM 4 BANKS X 4Mbit X 8 (804) 4 BANKS X 2Mbit X 16 (164) 4 BANKS X 8Mbit X 4 (404) 5 6 DDR400 DDR333 7.5 ns 7.5 ns Clock Cycle Time (tCK2.5) 6ns 6 ns Clock Cycle Time (tCK3) 5ns 6 ns 200 MHz 166 MHz Clock Cycle Time (tCK2)

Contextual Info: V58C2128 804/404/164 SB HIGH PERFORMANCE 128 Mbit DDR SDRAM 4 BANKS X 4Mbit X 8 (804) 4 BANKS X 2Mbit X 16 (164) 4 BANKS X 8Mbit X 4 (404) 5B 5 6 7 DDR400 DDR400 DDR333 DDR266 7.5 ns 7.5 ns 7.5 ns 7.5ns Clock Cycle Time (tCK2.5) 5ns 6ns 6 ns 7ns Clock Cycle Time (tCK3)

Contextual Info: V58C2128 804/404/164 SE HIGH PERFORMANCE 128 Mbit DDR SDRAM 4 BANKS X 4Mbit X 8 (804) 4 BANKS X 2Mbit X 16 (164) 4 BANKS X 8Mbit X 4 (404) 4 5 6 DDR500 DDR400 DDR333 7.5 ns 7.5 ns 7.5 ns Clock Cycle Time (tCK2.5) 5ns 6ns 6 ns Clock Cycle Time (tCK3) 4ns 5ns