M13S64164A Search Results

Contextual Info: ESMT M13S64164A Revision History Revision 0.1 23 Oct. 2006 - Original Revision 0.2 (06 Jun. 2007) - Add BGA type spec Revision 0.3 (20 Jul. 2007) - Modify BGA assignment Revision 0.4 (01 Oct. 2007) - Modify IDD spec. Revision 1.0 (20 Nov. 2007) - Delete “Preliminary”

Contextual Info: ESM T M13S64164A 2Y DDR SDRAM 1M x 16 Bit x 4 Banks Double Data Rate SDRAM Features Double-data-rate architecture, two data transfers per clock cycle Bi-directional data strobe (DQS) Differential clock inputs (CLK and CLK ) DLL aligns DQ and DQS transition with CLK transition

CKE 2009

Abstract: M13S64164A CL301
Contextual Info: ESMT M13S64164A Operation Temperature Condition -40°C~85°C DDR SDRAM 1M x 16 Bit x 4 Banks Double Data Rate SDRAM Features z JEDEC Standard z Internal pipelined double-data-rate architecture, two data access per clock cycle z Bi-directional data strobe DQS

Contextual Info: ESMT M13S64164A DDR SDRAM 1M x 16 Bit x 4 Banks Double Data Rate SDRAM Features z JEDEC Standard z Internal pipelined double-data-rate architecture, two data access per clock cycle z Bi-directional data strobe DQS z On-chip DLL z Differential clock inputs (CLK and CLK )

M13S64164A

Contextual Info: ESMT Preliminary M13S64164A Revision History Revision 0.1 23 Oct. 2006 - Original Revision 0.2 (06 Jun. 2007) - Add BGA type spec Revision 0.3 (20 Jul. 2007) - Modify BGA assignment Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007

DDR SDRAM

Abstract: BGA60 m13s64164a
Contextual Info: ESMT M13S64164A 2Y DDR SDRAM 1M x 16 Bit x 4 Banks Double Data Rate SDRAM Features z Double-data-rate architecture, two data transfers per clock cycle z Bi-directional data strobe (DQS) z Differential clock inputs (CLK and CLK ) z DLL aligns DQ and DQS transition with CLK transition

CKE 2009

Abstract: M13S64164A
Contextual Info: ESMT M13S64164A DDR SDRAM 1M x 16 Bit x 4 Banks Double Data Rate SDRAM Features z JEDEC Standard z Internal pipelined double-data-rate architecture, two data access per clock cycle z Bi-directional data strobe DQS z On-chip DLL z Differential clock inputs (CLK and CLK )

DDR SDRAM

Contextual Info: ESMT M13S64164A 2Y Automotive Grade DDR SDRAM 1M x 16 Bit x 4 Banks Double Data Rate SDRAM Features z Double-data-rate architecture, two data transfers per clock cycle z Bi-directional data strobe (DQS) z Differential clock inputs (CLK and CLK ) z DLL aligns DQ and DQS transition with CLK transition

Contextual Info: ESMT Preliminary M13S64164A Revision History Revision 0.1 23 Oct. 2006 - Original Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2006 Revision : 0.1 1/48 ESMT Preliminary M13S64164A DDR SDRAM 1M x 16 Bit x 4 Banks Double Data Rate SDRAM

Contextual Info: ESM T M13S64164A 2Y Automotive Grade DDR SDRAM 1M x 16 Bit x 4 Banks Double Data Rate SDRAM Features Double-data-rate architecture, two data transfers per clock cycle Bi-directional data strobe (DQS) Differential clock inputs (CLK and CLK ) DLL aligns DQ and DQS transition with CLK transition

DDR SDRAM

Contextual Info: ESMT M13S64164A 2Y Operation Temperature Condition -40°C~85°C DDR SDRAM 1M x 16 Bit x 4 Banks Double Data Rate SDRAM Features z Double-data-rate architecture, two data transfers per clock cycle z Bi-directional data strobe (DQS) z Differential clock inputs (CLK and CLK )

M13S2561616A-5TG

Abstract: 90-FBGA M12L64164A-7T M13S2561616A -5T M11B416256A-25JP diode 6BG 90FBGA M12L128168A-6TG M12L16161A TSOPII
Contextual Info: Product Selection Guide of ESMT DRAM Density 4Mb Updated Date : 11/06/2006 Organization Description 256Kb*16 EDO DRAM 5V EDO DRAM 5V EDO DRAM 3.3V EDO DRAM 3.3V Refresh 512 512 512 512 Speed 25ns 35ns 35ns 35ns Package Part Number Pb-free Sample MP Now Now