KM48S803 Search Results

Contextual Info: Preliminary SDRAM R evision H istory R evision 1 M ay 1998 - ICC2 N va lu e (10m A) is cha ng ed to 12m A. Revision .2 (June 1998) - tSH (-10 binning) is revised. REV. 2 June '98 ELECTRONICS Preliminary

KM48S8030BT

Contextual Info: KM48S8030B CMOS SDRAM 2M x 8Bit x 4 Banks Synchronous DRAM FEATURES GENERAL DESCRIPTION • • • • The KM48S8030B is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 8 bits, fabricated with SAMSUNG'S high performance CMOS technol­

KM48S8030BT

Contextual Info: KM48S8030B CMOS SDRAM Revision History Revision .3 November 1997 - tRDL has changed 10ns to 12ns. - Binning -10 does not meet PC100 characteristics . So AC parameter/Characteristics have changed to 64M 2nd values. Revision .4 (February 1998) - Input leakage Currents (Inputs / DQ) are changed.

KM48S8030D

Contextual Info: KM48S8030D CMOS SDRAM 64Mbit SDRAM 2M x 8Bit x 4 Banks Synchronous DRAM LVTTL Revision 0.0 May 1999 * Samsung Electronics reserves the right to change products or specification without notice. Rev. 0.0 May 1999 KM48S8030D CMOS SDRAM Revision History Revision 0.0 May 15, 1999

Contextual Info: KM48S8030B CMOS SDRAM Revision History Revision .3 N ovem ber 1997 - tRDL has changed 10ns to 12ns. - Binning -10 does not m eet PC100 characteristics . So AC param eter/C haracteristics have changed to 64M 2nd values. Revision .4 (February 1998) - Input leakage C urrents (Inputs / DQ) are changed.

KM48S8030AT

Abstract: M14e
Contextual Info: KM48S8030A CMOS SDRAM 2M x 8Bit x 4 Banks Synchronous DRAM FEATURES GENERAL DESCRIPTION . • •• rate Dynamic RAM organized as 4 x 2,097,152 words by 8 bits, fabricated with SAMSUNG'S high performance CMOS technol­ . . - JEDEC standard 3.3V power supply

16MX4

Abstract: KMM390S823DT1-GA samsung note
Contextual Info: SERIAL PRESENCE DETECT PC133 Registered DIMM Registered SDRAM PC133 DIMM 168pin SPD Specification REV. 1 July. 1999 REV. 1 July. '99 SERIAL PRESENCE DETECT PC133 Registered DIMM KMM390S823DT1-GA •Organization : 8MX72 •Composition : 8MX8 *9 •Used component part # : KM48S8030DT-GA

Contextual Info: Preliminary CMOS SDRAM KM48S8030C 2M x 8Bit x 4 Banks Synchronous DRAM FEATURES GENERAL DESCRIPTION • • • • The KM48S8030C is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 8 bits, fabricated with SAMSUNG'S high performance CMOS technol­

KM48S8030BT

Contextual Info: KM48S8030B CMOS SDRAM Revision History Revision .3 November 1997 - tRDL has changed 10ns to 12ns. - Binning -10 does not meet PC100 characteristics . So AC parameter/Characteristics have changed to 64M 2nd values. Revision .4 (February 1998) - Input leakage Currents (Inputs / DQ) are changed.

KM48S8030AT

Abstract: GD33 8030A
Contextual Info: KM48S8030AT SDRAM ELECTR ONICS 2M x 8Bit x 4 Bank Synchronous DRAM FEATURES GENERAL DESCRIPTION • JEDEC standard 3.3V Power Supply. • LVTTL/SSTL_3 Class II compatible with multiplexed address. • 4 banks operation. • MRS cycle with address key programs.

KM48S8030C

Contextual Info: KM48S8030C Preliminary CMOS SDRAM Revision History Revision 1 May 1998 - ICC2N value (10mA) is changed to 12mA. Revision .2 (June 1998) - tSH (-10 binning) is revised. REV. 2 June '98 Preliminary CMOS SDRAM KM48S8030C 2M x 8Bit x 4 Banks Synchronous DRAM

KM48S8030C

Abstract: KM48S803 PC133 1998
Contextual Info: KM48S8030C Preliminary PC133 CMOS SDRAM Revision History Revision 0.0 Oct., 1998 • PC133 first published. REV. 0 Oct. '98 Preliminary PC133 CMOS SDRAM KM48S8030C 2M x 8Bit x 4 Banks Synchronous DRAM FEATURES GENERAL DESCRIPTION • • • • The KM48S8030C is 67,108,864 bits synchronous high data

TC5118160

Abstract: msm-561 TMS444000 msm561 M5M418165 M5M418160 tms44c256 TC5117405 HY514264 HY514260
Contextual Info: New Page 1 DRAM 1Meg 1Mx1 256Kx4 FPM FPM Fujitsu MB81C100 MB81C4256 Goldstar GM71C100 GM71C4256 Hitachi HM511000 HM514256 Hyundai HY531000 HY534256 Micron MT4C1024 MT4C4256 Mitsubishi M5M41000 M5M44256 Nec UPD421000 UPD424256 Oki MSM511000 MSM514256 Samsung alt KM41C1000 KM44C256

Contextual Info: KMM374S823CTS PC100 Unbuffered DIMM Revision History Revision 0.1 Mar. 24, 1999 - Changed "Detail C" in PCB Dimension. - Changed decoupling capacitance from two 0.1uF to one 0.1uF and one 0.33 uF. Rev.0.1 Mar 1999 KMM374S823CTS PC100 Unbuffered DIMM KMM374S823CTS SDRAM DIMM

Contextual Info: PC66 SDRAM MODULE KMM374S1623BTL Revision History Revision .3 March 1998 Som e Param eter value s & C haracteristics of com p, level are changed as below : - Input leakage currents (Inputs) : ± 5 u A to ±1uA. - Input leakage currents (I/O) : ± 5 u A to ± 1 ,5uA.

Contextual Info: KMM374S1623BT PC100 SDRAM MODULE Revision History Revision .0 February 1998 - Input leakage Currents (Inputs / DQ) of Component level are changed. I IL(Inputs) : ± 5uA to ± 1uA, I IL(DQ) : ± 5uA to ± 1.5uA. - Cin to be measured at V DD = 3.3V, T A = 23°C, f = 1MHz, V REF =1.4V ± 200 mV.

Contextual Info: KMM374S1 623BT PC100 SDR AM M O D U L E Re vis ion Hist ory Revision .0 February 1998 -Input leakage Currents (Inputs / DQ) of Component level are changed. llL(lnputs) : ± 5uA to ± 1uA, llL(DQ) : ± 5uA to ± 1.5uA. -C in to be measured at V DD = 3.3V, T a = 23°C, f = 1MHz, V

Contextual Info: KMM366S823BTL PC66 SDRAM MODULE KMM366S823BTL SDRAM DIMM 8Mx64 SDRAM DIMM based on 8Mx8,4Banks, 4K Refresh, 3.3V Synchronous DRAMs with SPD GENERAL DESCRIPTION FEATURE The Samsung KMM366S823BTL is a 8M bit x 64 Synchronous Dynamic RAM high density memory module. The Samsung

Contextual Info: SDRAM MODULE Preliminary KMM377S823BT1 Revision History Revision 3 May 1998 - CLK Input Cap. is added by PLL Input Cap. (24pF) Revision 4 (July 1998) - "REGE" description is changed. Revision 5 (Aug. 1998) - Package Dimension changed. REV. 5 Aug. 1998 Preliminary

KM48S8030

Abstract: KMM350S823BT1-GL
Contextual Info: SDRAM MODULE Preliminary KMM350S823BT1 Revision History Revision 3 July 1998 - "REGE" description is changed. Revision 4 ( Aug. 1998) - Package Dimension changed REV. 4 Aug. 1998 Preliminary KMM350S823BT1 SDRAM MODULE KMM350S823BT1 SDRAM DIMM (Intel 1.0 ver. Base)

KM48S8030BT-G10

Abstract: KM48S8030BT KM48S8030BT-G
Contextual Info: KMM374S823BTL PC66 SDRAM MODULE Revision History Revision .3 Mar. 1998 •Some Parameter values & Characteristics of comp. level are changed as below : - Input leakage currents (Inputs) : ±5uA to ±1uA. - Input leakage currents (I/O) : ±5uA to ±1.5uA.

KMM375S1723T-G0

Abstract: KMM375S1723T-G8 KMM375S1723T-GH KMM375S1723T-GL
Contextual Info: Preliminary KMM375S1723T SDRAM MODULE KMM375S1723T SDRAM DIMM 16Mx72 SDRAM DIMM with PLL & Register based on 16Mx8, 4Banks 4K Ref., 3.3V Synchronous DRAMs with SPD GENERAL DESCRIPTION FEATURE The Samsung KMM375S1723T is a 16M bit x 72 Synchronous Dynamic RAM high density memory module. The Samsung KMM375S1723T consists of nine CMOS 16Mx8 bit

KMM374S823DTS-GA

Contextual Info: KMM374S823DTS PC133 Unbuffered DIMM Revision History Revision 0.0 May, 1999 • PC133 first published. REV. 0 May 1999 KMM374S823DTS PC133 Unbuffered DIMM KMM374S823DTS SDRAM DIMM 8Mx72 SDRAM DIMM with ECC based on 8Mx8, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs with SPD

Contextual Info: KMM466S823DT3 PC66 SODIMM Revision History Revision 0.0 July 5, 1999 • Changed tRDL from 1CLK to 2CLK in OPERATING AC PARAMETER. • Skip ICC4 value of CL=2 in DC characteristics in datasheet. • Define a new parameter of tDAL( 2CLK +20ns), Last data in to Active delay in OPERATING AC PARAMETER.