JEDEC 2A Search Results

SMD Packages

Contextual Info: IPC/JEDEC J-STD-033A July 2002 Supersedes IPC/JEDEC J-STD-033 April 1999 JOINT INDUSTRY STANDARD Handling, Packing, Shipping and Use of Moisture/Reflow Sensitive Surface Mount Devices NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of

1N5171

Abstract: 1N5172 mh70 2A200 Solitron 2a200 1N5176
Contextual Info: rectifiers 19 2A SERIES JEDEC REGISTRATION CASE STYLE 1N5170 thru 1N5178 1N4517 G Solitron Part Numbers Jedec Type !. PIV Jedec Type PIV 15 N/A MCV 15 N/A 2A30 30 N/A MC30 30 1N5171 2A50 50 N/A M67 50 1N5172 2A100 100 N/A MH67 50 1N4517 2A200 200 N/A M68

29f040c-90

Abstract: 29F040C70 29F040C-70
Contextual Info: FLASH MEMORY CMOS ;. M B M 29 F040C-70/-90 FEATURES Single 5.0 V read, program and erase Minimizes system level power requirements Compatible with JEDEC-standard commands Uses same software commands as EzPROMs Compatible with JEDEC-standard byte-wide pinouts

Contextual Info: ? BMI FUJITSU SEMICONDUCTOR DATA SHEET • DISTINCTIVE CHARACTERISTICS • Single 5.0 V read, write, and erase Minimizes system level power requirements • Compatible with JEDEC-standard commands Uses same software commands as E2PROMs • Compatible with JEDEC-standard word-wide pinouts

EE1004

Contextual Info: M34E04 4-Kbit Serial Presence Detect SPD EEPROM compatible with JEDEC EE1004 Datasheet - production data Features • 512-byte Serial Presence Detect EEPROM compatible with JEDEC EE1004 specification • Compatible with SMBus serial interface: – up to 1 MHz transfer rate

Contextual Info: • DISTINCTIVE CHARACTERISTICS * Single 5.0 V read, write and erase Minimizes system level power requirements * Compatible with JEDEC-standard commands Uses same software commands as E2PRO!\/ls a -ym 1 Compatible with JEDEC-standard byte-wide pinoutjm 32-pin PLCC Package suffix: PD

SMP30-100

Abstract: SMP30-120 SMP30-130 SMP30-180 SMP30-200 SMP30-220 SMP30-62 SMP30-68 crowbar 2kV 38a sma package
Contextual Info: SMP30-xxx Series TRISILTM PRELIMINARY DATASHEET FEATURES BIDIRECTIONAL CROWBAR PROTECTION. VOLTAGE RANGE: FROM 62 V TO 270 V. HOLDING CURRENT : IH = 150 mA min. REPETITIVE PEAK PULSE CURRENT : IPP = 30 A, 10/1000 µs. JEDEC REGISTERED PACKAGE OUTLINE SMA JEDEC DO-214AA

Contextual Info: FLASHMEMORY CMOS MBM29F4ÖÖTÄ#o/Äi 2/MBM29F400 • FEATURES • Single 5.0 V read, write, and erase Minimizes system level power requirements • Compatible with JEDEC-standard commands Uses same software commands as EzPROMs • Compatible with JEDEC-standard world-wide pinouts

MBM29F200BA

Contextual Info: FLASH MEMORY CMOS 9F2OOTA-70/-90/-12/M B QBA-70/-90/-12 FEATURES • Single 5.0 V read, write, and erase Minimizes system level power requirements • Compatible with JEDEC-standard commands Uses same software commands as E2PROMs • Compatible with JEDEC-standard world-wide pinouts

Contextual Info: LP2998/LP2998-Q1 www.ti.com SNVS521J – DECEMBER 2007 – REVISED DECEMBER 2013 LP2998/LP2998-Q1 DDR-I and DDR-II Termination Regulator Check for Samples: LP2998/LP2998-Q1 FEATURES DESCRIPTION • The LP2998 linear regulator is designed to meet JEDEC SSTL-2 and JEDEC SSTL-18 specifications

Contextual Info: LP2998/LP2998-Q1 www.ti.com SNVS521J – DECEMBER 2007 – REVISED DECEMBER 2013 LP2998/LP2998-Q1 DDR-I and DDR-II Termination Regulator Check for Samples: LP2998/LP2998-Q1 FEATURES DESCRIPTION • The LP2998 linear regulator is designed to meet JEDEC SSTL-2 and JEDEC SSTL-18 specifications

Contextual Info: LP2998/LP2998-Q1 www.ti.com SNVS521J – DECEMBER 2007 – REVISED DECEMBER 2013 LP2998/LP2998-Q1 DDR-I and DDR-II Termination Regulator Check for Samples: LP2998/LP2998-Q1 FEATURES DESCRIPTION • The LP2998 linear regulator is designed to meet JEDEC SSTL-2 and JEDEC SSTL-18 specifications

74HCT08

Abstract: 74HC08 74hct08 philips 74HC08D 74HC08DB 74HC08N 74HCT08D 74HCT08N MNA221 SC-501-14
Contextual Info: Philips Semiconductors Product specification Quad 2-input AND gate 74HC08; 74HCT08 FEATURES DESCRIPTION • Complies with JEDEC standard no. 8-1A The 74HC/HCT08 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL LSTTL . They are specified in compliance with JEDEC

Contextual Info: DISTINCTIVE CHARACTERISTICS • Single 3.0 V read, write, and erase Minimizes system level power requirements • Compatible with JEDEC-standard commands Uses same software commands as E2PROMs • Compatible with JEDEC-standard word-wide pinouts 48-pin TSOP Package suffix: PFTN - Normal Bend Type, PFTR - Reversed Bend Type

29F800TA

Abstract: 29f800ba MBM29F800 29F800T
Contextual Info: • FEATURES • Single 5.0 V read, write, and erase Minimizes system level power requirements • Compatible with JEDEC-standard commands Uses same software commands as E2PROMs • Compatible with JEDEC-standard world-wide pinouts 48-pin TSOP I (Package suffix: PFTN - Normal Bend Type, PFTR - Reversed Bend Type)

74HC08

Abstract: 74HCT08 74HC08D 74HC08DB 74HC08N 74HCT08D 74HCT08N
Contextual Info: Philips Semiconductors Product specification Quad 2-input AND gate 74HC08; 74HCT08 FEATURES DESCRIPTION • Complies with JEDEC standard no. 8-1A The 74HC/HCT08 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL LSTTL . They are specified in compliance with JEDEC

Contextual Info: FLASH MEMORY CMOS 2M 256K x 8 BIT MBM29LV002Tio-12/MBM29LV002B-10 12 • FEATURES • Single 3.0 V read, program, and erase Minimizes system level power requirements • Compatible with JEDEC-standard commands Uses same software commands as E2PROMs • Compatible with JEDEC-standard world-wide pinouts

MBM29LV002B

Contextual Info: FLASH MEMORY CMOS 2M 256K x 8 BIT MBM29LV002T-1 0.-12/M BM29LV002B-10-12 • FEATURES • Single 3.0 V read, program, and erase Minimizes system level power requirements • Compatible with JEDEC-standard commands Uses same software commands as E2PROMs • Compatible with JEDEC-standard world-wide pinouts

Contextual Info: FLASH MEMORY Tm 128K X 8 B TI MBM29LV001 TC-ss -7o/MBM29LV001 BC-ss -70 • FEATURES • Single 3.0 V read, program, and erase Minimizes system level power requirements • Compatible with JEDEC-standard commands Uses same software commands as E2PROMs • Compatible with JEDEC-standard world-wide pinouts

Contextual Info: FLASHMEMORY CMOS • FEATURES • Single 5.0 V read, write, and erase Minimizes system level power requirements • Compatible with JEDEC-standard commands Uses same software commands as E2PROMs • Compatible with JEDEC-standard world-wide pinouts 48-pin TSOP Package suffix: PFTN - Normal Bend Type, PFTR - Reversed Bend Type

MBM29LV002B

Contextual Info: FLASH MEMORY . M 2 FEATURES • Single 3.0 V read, program, and erase Minimizes system level power requirements • Compatible with JEDEC-standard commands Uses same software commands as E2PROMs • Compatible with JEDEC-standard world-wide pinouts 40-pin TSOP Package suffix: PTN - Normal Bend Type, PTR - Reversed Bend Type

Contextual Info: TC74VHC123,221AFN TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74VHC123AFN,TC74VHC221AFN Dual Monostable Multivibrator TC74VHC123AFN TC74VHC221AFN Retriggerble Non-Retriggerble Note: xxxFN JEDEC SOP is not available in Japan. TC74VHC123AFN, TC74VHC221AFN

G2992B

Contextual Info: G2992B Global Mixed-mode Technology 2A DDR Bus Termination Regulator Features General Description „ The G2992B is a linear regulator designed to meet the JEDEC SSTL-18, SSTL-2 and SSTL-3 Series Stub Termination Logic specifications for termination of DDR

Contextual Info: ISSUE NO : Rev: 001 Product Family Data Sheet LM231B - 2323 Middle Power LED Introduction Features Package : Silicone Reflector LED Package Beam Angle: 120˚ Precondition : JEDEC Level 2a Dimension : 2.3 x 2.3 x 0.7 mm ESD withstand Voltage : up to ± 5KV [HBM]