JEDEC 16 Search Results
JEDEC 16 Result Highlights (5)
| Part | ECAD Model | Manufacturer | Description | Download | Buy |
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| TMP139AIYAHR | Texas Instruments | JEDEC DDR5 temperature sensor with 0.5 °C accuracy 6-DSBGA -40 to 125 |
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| SN74SSQEA32882ZALR | Texas Instruments | JEDEC SSTE32882 Compliant 28-Bit to 56-Bit Registered Buffer with Address-Parity Test 176-NFBGA 0 to 85 |
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| SN74SSQE32882ZALR | Texas Instruments | JEDEC SSTE32882 Compliant 28-Bit to 56-Bit Registered Buffer with Address-Parity Test 176-NFBGA 0 to 85 |
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| SN74SSQEB32882ZALR | Texas Instruments | JEDEC SSTE32882 Compliant 28-Bit to 56-Bit Registered Buffer with Address-Parity Test 176-NFBGA 0 to 85 |
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| SN74SSQEC32882ZALR | Texas Instruments | JEDEC SSTE32882 Compliant Low Power 28-Bit to 56-Bit Registered Buffer with Address-Parity Test 176-NFBGA 0 to 85 |
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JEDEC 16 Datasheets Context Search
| Catalog Datasheet | Type | Document Tags | |
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P16HD8
Abstract: P16R4 preload decade counter transistor B1010 F159
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reset22ap16hd8p16r4preload decade counter+2 | |
AS4C32M16D2Contextual Info: AS4C32M16D2 512M 32M x 16 bit DDRII Synchronous DRAM (SDRAM) Confidential Advanced (Rev. 1.1, Feb. /2013) Features Overview • JEDEC Standard Compliant JEDEC standard 1.8V I/O (SSTL_18-compatible) Power supplies: VDD & VDDQ = +1.8V 0.1V Supports JEDEC clock jitter specification |
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as4c32m16d218-compatiblelat19 | |
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Contextual Info: AS4C32M16D2 512M 32M x 16 bit DDRII Synchronous DRAM (SDRAM) Confidential Advanced (Rev. 1.1, Feb. /2013) Features Overview • JEDEC Standard Compliant JEDEC standard 1.8V I/O (SSTL_18-compatible) Power supplies: VDD & VDDQ = +1.8V 0.1V Supports JEDEC clock jitter specification |
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as4c32m16d218-compatiblelat19 | |
TOSHIBA el suffix
Abstract: jedec MS-012-AC EIA and EIAJ standards jedec EIAJ EIAJ standards FS 20.00 p SOL20 package SOL16-P SOL16 package
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sol14-p-150sol16-p-150sol20-p-300op14-p-300+16 | |
SMD PackagesContextual Info: IPC/JEDEC J-STD-033A July 2002 Supersedes IPC/JEDEC J-STD-033 April 1999 JOINT INDUSTRY STANDARD Handling, Packing, Shipping and Use of Moisture/Reflow Sensitive Surface Mount Devices NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of |
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j-std-033aj-std-033smd packages | |
JESD-21C
Abstract: JESD21-C JESD8-15
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cu877jesd82-82200pf2506036017y0+4 | |
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Contextual Info: JEDEC JESD204A data converter interface Technical analysis Rev. 2.1 — 14 October 2011 White paper Document information Info Content Keywords JEDEC JESD204A, High-speed data converters Abstract This report describes the technical details of JEDEC JESD204A interface |
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jesd204a | |
JESD204
Abstract: GSM transmitter receiver spartan hdmi JESD204A 4bit serializer abstract
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jesd204a10galjesd204gsm transmitter receiver+2 | |
JEDEC J-STD-020C
Abstract: JESD47 Reliability Test Methods for Packaged Devices Infineon moisture sensitive package JESD-47 JESD22-A120 AMD reflow soldering profile BGA J-STD-035 semiconductors cross reference ipc-sm-786A
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j-std-020cj-std-020b1-580987-46-xjedec j-std-020c+9 | |
Reflow
Abstract: JEDEC J-STD-020d.1 JEP-140 JEP140 J-STD-035 JESD22-B112 JEDEC J-STD-020d JESD47 JESD22-B108 IPC-020d-5-1
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j-std-020dreflowjedec j-std-020d.1jep-140+7 | |
2N6583
Abstract: 2N6736
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2n62762n62772n62782n6279+8 | |
AN9321
Abstract: HUFA75617D3 HUFA75617D3S HUFA75617D3ST TB334
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hufa75617d3hufa75617d3so-251aao-252aa+4 | |
MS-010Contextual Info: JEDEC Publication No. 95 Page _ JEDEC Publication No. 95 Page _ SECTION Z - Z DATUM - A - (DATUM — A - ) EVEN NUMBER LEADS (DIMENSIONS IN INCHES) JEDEC SOUD STATE PRODUCT OUTLINES ODD NUMBER LEADS DETAIL A TITLE dual in lin e PLASTIC FAMILY (R -P D IP -T ) |
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ms-010 | |
80386SLContextual Info: 1C Test Clips Pomona JEDEC PQFP Test Clips Pomona's JEDEC QFP test clips are designed to fit on surface-mounted plastic and ceramic JEDEC chips. Choose from three clip types designed to give you optimum func tionality and ease of use for testing, troubleshooting |
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80386sl | |
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Contextual Info: Industrial Temperature 16Mbit Enhanced Synchronous DRAM 1Mx16 ESDRAM Preliminary Data Sheet Features Description • • As a JEDEC superset standard, the Enhanced Synchronous DRAM ESDRAM is an evolutionary modification to the JEDEC standard SDRAM. The industrial temperature grade |
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16mbit1mx16sm2404t-750-pin+2 | |
EM68B16CWQC
Abstract: EM68B16C EM68B16CWQC-25H 6-10PER EM68B16 DDR2-667 DDR2-800 EM68B16CW
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em68b16cwqc18-compatible333/400mhz84-ball+7 | |
EM68B16CWPA
Abstract: EM68B16CWPA-25H EM68B16C Etron DDR2-667 DDR2-800 2TWR EM68B16CWPA25H
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em68b16cwpa18-compatible333/400mhz84-ball+7 | |
EM68A16CWQB-25H
Abstract: EM68A16CWQB 2TWR EM68A Etron em68a16
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em68a16cwqb18-compatible333/400mhz84-ball+5 | |
AN7254
Abstract: AN9321 AN9322 HUF75617D3 HUF75617D3S HUF75617D3ST TB334
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huf75617d3huf75617d3so-251aao-252aa+6 | |
GP021
Abstract: Photo Flash Rectifiers gp02-12 GP02 GP02-25 GP02-30 GP05 GP05-10 GP05-16 GP05-18
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gp05seriesd0-15d0-41gp021+9 | |
Photo Flash Rectifiers
Abstract: GP-024-5 gp02-12 GP021 GP02 GP02-20 GP05 GP05-10 GP05-15 GP05-16
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gp05seriesd0-15d0-41photo flash rectifiers+9 | |
112E1
Abstract: 75617D AN9321 AN9322 HUF75617D3 HUF75617D3S HUF75617D3ST TB334
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huf75617d3huf75617d3so-251aao-252aa+6 | |
AS4C64M16D2Contextual Info: AS4C64M16D2 1Gb 64M x 16 bit DDRII Synchronous DRAM (SDRAM) Alliance Memory Confidential Advanced (Rev. 1.0 April 2012) Features Overview • JEDEC Standard Compliant • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Power supplies: VDD & VDDQ = +1.8V ± 0.1V |
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as4c64m16d218-compatible400mhz16bit | |
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Contextual Info: DIMM Socket for Memory Expansion Conforming to JEDEC standard DMM Series, 168 contacts CjT>T>fc.j APPLICATION Workstations, Computers, Disk arrays and Servers FEATURES •Applicable to 168-position module per JEDEC standard MO-161 • Board locks which prevent the |
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168-positionmo-161ul94v-0dmm-168a-xxxxx+4 | |