JESD204 Search Results

JESD204

Abstract: JESD204A AN10812
Contextual Info: AN10812 JESD204A: New serialization technique for high speed data converters Rev. 01 — 26 May 2009 Application note Document information Info Content Keywords JESD204A, Data Converters, Data rate, EMC, EMI Abstract This document gives a high level description of the JESD204A

JESD204A

Abstract: WIDEBAND ULTRASOUND CMLAN
Contextual Info: NXP dual 12/14-bit ADC with serial interface ADC1x13 Dual-channel ADCs with JESD204A-compliant outputs for wireless and industrial Equipped with 3.125-Gbps serial output interfaces that comply with JEDEC JESD204A, these dual-channel ADCs support sample rates up to 125 MSPS, integrate a programmable gain buffer,

Contextual Info: DAC1653Q/DAC1658Q Quad 16-bit DAC: 10 Gbps JESD204B interface: x2, x4 and x8 interpolating Advance data sheet Revision 2.3.1 1. GENERAL DESCRIPTION DAC1653Q and DAC1658Q are high-speed, high-performance 16-bit quad channel Digital-to-Analog Converters DACs .

Contextual Info: Product Folder Sample & Buy Technical Documents Support & Community Tools & Software ADC16DX370 SNVSA18B – APRIL 2014 – REVISED APRIL 2014 ADC16DX370 Dual 16-Bit 370 MSPS ADC With 7.4 Gb/s JESD204B Outputs 1 Features 3 Description • • • • The ADC16DX370 device is a monolithic dualchannel high performance analog-to-digital converter

pfc8574

Abstract: ENC 03 LTC2272 marking code s4 diode op amp marking P3 JESD204 LTC2273
Contextual Info: LTC2273/LTC2272 16-Bit, 80Msps/65Msps Serial Output ADC DESCRIPTION FEATURES n High Speed Serial Interface JESD204 Sample Rate: 80Msps/65Msps 77.7dBFS Noise Floor 100dB SFDR SFDR >90dB at 140MHz (1.5VP-P Input Range) PGA Front End (2.25VP-P or 1.5VP-P Input Range)

AD9250

Abstract: E19 CORE TRANSFORMER AD9524 upstream docsis cmts JESD204B
Contextual Info: 14-Bit, 170 MSPS/250 MSPS, JESD204B, Dual Analog-to-Digital Converter AD9250 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM DVDD AGND DGND DRGND AD9250 VIN+A VIN–A PIPELINE 14-BIT ADC VCM VIN+B VIN–B PIPELINE 14-BIT ADC JESD-204B INTERFACE SERDOUT0± CML, TX

Contextual Info: UM10435 DAC1x08WO demonstration board Rev. 01.00 — 30 septembre 2010 User manual Document information Info Content Keywords JESD204A, PCB2134, DAC, LabView, FPGA, Altera, Xilinx, Lattice Abstract This document describes the use of DAC1408D650WO/DB, DAC1208D650WO/DB, DAC1008D650WO/DB, DAC1408D750WO/DB,

LMK04828BISQE

Abstract: LMK04828B
Contextual Info: LMK04826B, LMK04828B www.ti.com SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 LMK0482xB Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner with Dual Loop PLLs Check for Samples: LMK04826B, LMK04828B 1 INTRODUCTION 1.1 Features 12 • JEDEC JESD204B Support

JESD204A

Abstract: PH01 PH03 fpga based Numerically Controlled Oscillator
Contextual Info: DAC1208D750 Dual 12-bit DAC; up to 750 Msps; 2x 4× or 8× interpolating with JESD204A interface Rev. 1 — 5 October 2010 Objective data sheet 1. General description The DAC1208D750 is a high-speed 12-bit dual channel Digital-to-Analog Converter DAC with selectable 2×, 4× or 8× interpolating filters optimized for multi-carrier WCDMA

DAC1408D650

Abstract: diode ph03 JESD204A PH01 PH03
Contextual Info: DAC1408D650 Dual 14-bit DAC; up to 650 Msps; 2, 4 or 8 interpolating with JESD204A interface Rev. 4 — 26 November 2010 Product data sheet 1. General description The DAC1408D650 is a high-speed 14-bit dual channel Digital-to-Analog Converter DAC with selectable 2, 4 or 8 interpolating filters optimized for multi-carrier WCDMA

how dsp is used in radar

Abstract: JESD204 JESD204A Application of dsp in radar nxp proximity antenna design JESD204B beam steering DAC1408D radar front end Altera Stratix V
Contextual Info: JESD204A for wireless base station and radar systems November 2010 Maury Wood- NXP Semiconductors Deepak Boppana, Ian Land - Altera Corporation 0.0 Introduction - New trends for wireless base station and radar systems Digital Signal Processing DSP technology continues to transform radar systems and

JESD204

Abstract: GSM transmitter receiver spartan hdmi JESD204A 4bit serializer abstract
Contextual Info: R_10002 Technical analysis of the JEDEC JESD204A data converter interface Rev. 01 — 12 April 2010 Document information Info Content Keywords JEDEC JESD204A, High-speed data converters Abstract Report R_10002 NXP Semiconductors Technical analysis of the JEDEC JESD204A data converter interface

JESD204A

Abstract: JESD204 8B10B
Contextual Info: AN10812 JESD204A: High speed serialization for data converters Rev. 2 — 23 September 2010 Application note Document information Info Content Keywords JESD204A, Data converters, Data rate, EMC, EMI Abstract This document gives a high level description of the JESD204A

Contextual Info: JEDEC JESD204A data converter interface Technical analysis Rev. 2.1 — 14 October 2011 White paper Document information Info Content Keywords JEDEC JESD204A, High-speed data converters Abstract This report describes the technical details of JEDEC JESD204A interface

Contextual Info: DAC1653Q/DAC1658Q Quad 16-bit DAC: 10 Gbps JESD204B interface: up to 1.50 Gsps; x2, x4 and x8 interpolating Rev. 1.03 — 13 May 2013 Advance data sheet 1. General description The DAC1658Q and the DAC1653Q are high-speed high-performance 16-bit quad channel digital-to-analog converter DAC with high and low common-mode output. The

Contextual Info: 12-Bit, 1 GSPS JESD204B, Dual Analog-to-Digital Converter AD9234 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM APPLICATIONS Communications Diversity multiband, multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE Point-to-point radio systems Digital predistortion observation path

HVQFN-56

Contextual Info: DAC1628D1G25 Dual 16-bit DAC: JESD204B interface: up to 1.25 Gsps; x2, x4 and x8 interpolating Rev. 1.1 — 10 October 2011 Objective data sheet 1. General description The DAC1628D1G25 is a high-speed high-performance 16-bit dual channel digital-to-analog converter DAC . The device provides a sample rate up to 1.25 Gsps with

082D

Contextual Info: ADC1213S series Single 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; serial JESD204A interface Rev. 2 — 9 June 2011 Product data sheet 1. General description The ADC1213S is a single channel 12-bit Analog-to-Digital Converter ADC optimized for high dynamic performance and low power at sample rates up to 125 Msps. Pipelined

PRBS31

Contextual Info: ADC1213S series Single 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; serial JESD204A interface Rev. 1 — 14 March 2011 Product data sheet 1. General description The ADC1213S is a single channel 12-bit Analog-to-Digital Converter ADC optimized for

Contextual Info: Product Folder Sample & Buy Support & Community Tools & Software Technical Documents LMK04821, LMK04826, LMK04828 SNAS605AQ – MARCH 2013 – REVISED AUGUST 2014 LMK0482x Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner with Dual Loop PLLs 1 Features

Contextual Info: ADC1113S125 Single 11-bit ADC; serial JESD204A interface Rev. 1 — 15 March 2011 Product data sheet 1. General description The ADC1113S125 is a single channel 11-bit Analog-to-Digital Converter ADC optimized for high dynamic performance and low power at a sample rate of 125 Msps. Pipelined

Contextual Info: ADS61JB23 www.ti.com SLOS755 – DECEMBER 2012 12-Bit Input-Buffered 80 MSPS ADC with JESD204A Output Interface Check for Samples: ADS61JB23 FEATURES APPLICATIONS • • • 1 • • • • • • • • • Output Interface: – Single-Lane and Dual-Lane Interfaces

Contextual Info: DAC1208D650 Dual 12-bit DAC; up to 650 Msps; 2, 4 or 8 interpolating with JESD204A interface Rev. 3 — 31 January 2012 Product data sheet 1. General description The DAC1208D650 is a high-speed 12-bit dual channel Digital-to-Analog Converter DAC with selectable 2, 4 or 8 interpolating filters optimized for multi-carrier WCDMA

Contextual Info: DAC1008D750 Dual 10-bit DAC; up to 750 Msps; 2, 4 or 8 interpolating with JESD204A interface Rev. 3 — 31 January 2012 Product data sheet 1. General description The DAC1008D750 is a high-speed 10-bit dual channel Digital-to-Analog Converter DAC with selectable 2, 4 or 8 interpolating filters optimized for multi-carrier WCDMA