PRBS31 Search Results

Contextual Info: DS125DF111 www.ti.com SNLS450 – JANUARY 2014 DS125DF111 Multi-Protocol 2-Channel 9.8 - 12.5 Gb/s Retimer Check for Samples: DS125DF111 FEATURES DESCRIPTION • The DS125DF111 is a dual channel 1-lane bidirectional retimer with integrated signal conditioning. The DS125DF111 includes an input

Contextual Info: Finisar Product Specification RoHS-6 Compliant 10Gb/s DWDM 40km Multi-Rate XFP Optical Transceiver FTLX3611M3xx PRODUCT FEATURES • Supports 9.95Gb/s to 11.1Gb/s bit rates • Hot-pluggable XFP footprint • Maximum link length of 40km • Temperature-stabilized DWDMrated EML transmitter

Contextual Info: Finisar PRELIMINARY Product Specification RoHS-6 Compliant 10Gb/s DWDM 40km Multi-Rate XFP Optical Transceiver FTLX3611M3xx PRODUCT FEATURES • Supports 9.95Gb/s to 11.1Gb/s bit rates • Hot-pluggable XFP footprint • Maximum link length of 40km • Temperature-stabilized DWDMrated EML transmitter

Contextual Info: Finisar PRELIMINARY Product Specification 10Gb/s DWDM 40km XFP Optical Transceiver FTRX-3611-3xx PRODUCT FEATURES • Supports 9.95Gb/s to 10.7Gb/s bit rates • Hot-pluggable XFP footprint • Maximum link length of 40km • Temperature-stabilized DWDMrated EML transmitter

Contextual Info: Finisar PRELIMINARY Product Specification 10Gb/s DWDM 80km XFP Optical Transceiver FTRX-3811-3xx PRODUCT FEATURES • Supports 9.95Gb/s to 10.7Gb/s bit rates • Hot-pluggable XFP footprint • Maximum link length of 80km • Temperature-stabilized DWDMrated EML transmitter

Contextual Info: Finisar PRELIMINARY Product Specification RoHS-6 Compliant 10Gb/s DWDM 80km Multi-Rate XFP Optical Transceiver FTLX3811M3xx D PRODUCT FEATURES • Supports 9.95Gb/s to 11.1Gb/s bit rates • Hot-pluggable XFP footprint • Maximum link length of 80km • RoHS-6 compliant lead-free

OC48

Abstract: SSTL-15 SSTL-18
Contextual Info: Arria II Device Handbook Volume 3: Device Datasheet and Addendum Arria II Device Handbook Volume 3: Device Datasheet and Addendum 101 Innovation Drive San Jose, CA 95134 www.altera.com AIIGX5V3-4.0 Document last updated for Altera Complete Design Suite version:

Contextual Info: DAC1653Q/DAC1658Q Quad 16-bit DAC: 10 Gbps JESD204B interface: x2, x4 and x8 interpolating Advance data sheet Revision 2.3.1 1. GENERAL DESCRIPTION DAC1653Q and DAC1658Q are high-speed, high-performance 16-bit quad channel Digital-to-Analog Converters DACs .

10 Gbps Modulator Driver

Abstract: S0319
Contextual Info: ONET1101L www.ti.com SLLS883 – MARCH 2008 11.3 Gbps Laser Diode Driver FEATURES 1 • • • • • • • • • • Up to 11.3 Gbps Operation Two-Wire Digital Interface Digitally Selectable Modulation Current up to 80 mA Digitally Selectable Bias Current up to 100 mA

RSX2

Contextual Info: ONET8501PB www.ti.com . SLLS910 – JULY 2008 11.3-Gbps RATE-SELECTABLE LIMITING AMPLIFIER

Contextual Info: ONET8531T www.ti.com SLLS891 – FEBRUARY 2008 11.3 Gbps Limiting Transimpedance Amplifier With RSSI FEATURES APPLICATIONS • • • • • • • • 1 • • • • • • • • 10 GHz Bandwidth 4.5 kΩ Differential Small Signal Transimpedance

10G APD

Abstract: Transponder PPM FTLX1841 FTLX1841E2 PRBS31
Contextual Info: Product Specification RoHS-6 Compliant 10Gb/s 1550nm Single Mode Datacom X2 ZR Transponder FTLX1841E2 PRODUCT FEATURES ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ Hot pluggable X2 MSA form factor Total power consumption: 4.0 W maximum RoHS-6 compliant lead-free

sem 2106

Abstract: SR5690 Northbridge Southbridge PCIe Bridge RD890 5650 ati ACC MICRO 2178 Index
Contextual Info: AMD SR5690/5670/5650 Register Reference Guide Publication # 43871 Issue Date: May 2012 Revision: 3.03 Trademarks AMD, the AMD Arrow logo, ATI, and combinations thereof, are trademarks of Advanced Micro Devices, Inc. HyperTransport is a licensed trademark of the HyperTransport Technology Consortium.

UG366

Abstract: XC6VLX75T-FF784 aurora GTX XC6VLX240T-FF1759 verilog code of prbs pattern generator XC6VLX130T-FF784 XC6VSX475T-FF XC6VLX240T-FF784 XC6VLX130T FF1156
Contextual Info: Virtex-6 FPGA GTX Transceivers User Guide UG366 v2.2 February 23, 2010 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the

equalizer circuit diagram

Abstract: AN-1187 DS32EV100 DS32EV100SD DS32EV100SDX PRBS-31
Contextual Info: DS32EV100 Programmable Single Equalizer General Description Features The DS32EV100 programmable equalizer provides compensation for transmission medium losses and reduces the medium-induced deterministic jitter for NRZ data channel. The DS32EV100 is optimized for operation up to 3.2 Gbps for both

SDA14

Abstract: PRBS7
Contextual Info: DS32EV100 Programmable Single Equalizer General Description Features The DS32EV100 programmable equalizer provides compensation for transmission medium losses and reduces the medium-induced deterministic jitter for NRZ data channel. The DS32EV100 is optimized for operation up to 3.2 Gbps for both

Achronix Semiconductor

Contextual Info: I Speedster22i HD FPGA Family DS004 Rev. 2.6 – May 8, 2014 Preliminary Highlights • • • Advanced highest-density and highest‐bandwidth FPGA • Over 1.7 million effective look‐up‐tables • Abundant embedded hard IP for communica‐

cd 1619 CP

Abstract: RX SOP 1738 bc 494 b f.m transmitter Schematics AL 1450 DV hp 2212 sdc 2025 AL 2450 dv circuit diagram toggle switches 2041 BY TRANSISTOR BC 187 vhdl code for 16 prbs generator
Contextual Info: Stratix II GX Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com SIIGX5V1-4.2 Copyright 2007 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and

NELCO-4000-13

Abstract: hfss tdr HFTA-05 AN-596-1 Nelco4000-13 pcb fabrication process Nelco-4000 backplane design card fci 10Gbase-kr backplane connector
Contextual Info: AN 596: Modeling and Design Considerations for 10 Gbps Connectors AN-596-1.0 March 2010 This application note discusses the impact of backplane connectors on a 10 Gbps serial channel performance. It demonstrates how to project the connector’s impact at

verilog code of prbs pattern generator

Abstract: dma controller VERILOG LED Dot Matrix vhdl code vhdl code for 16 prbs generator QII53027-10 prbs pattern generator using vhdl free verilog code of prbs pattern generator logic analyzer AR22 PRBS23
Contextual Info: Section IV. System Debugging Tools The Altera Quartus® II design software provides a complete design debugging environment that easily adapts to your specific design requirements. This handbook is arranged in chapters, sections, and volumes that correspond to the major tools

crpa

Abstract: HD-SDI over sdh SSTL-15 HIV54001-1 SSTL-18 HC4GX35FF1517N M144K
Contextual Info: HardCopy IV Device Handbook, Volume 4 101 Innovation Drive San Jose, CA 95134 www.altera.com HC4_H5V4-1.0 Copyright 2009 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other

laser diode FP TO for SFP

Abstract: TOSA Mbps SLT2486 AN-743 ADuC70xx automatic DFB laser power control VCSEL die ADN2870 NX7315UA OC48
Contextual Info: 3.3 V Dual-Loop, 50 Mbps to 3.3 Gbps Laser Diode Driver ADN2870 FEATURES GENERAL DESCRIPTION SFP/SFF and SFF-8472 MSA-compliant SFP reference design available 50 Mbps to 3.3 Gbps operation Multirate 155 Mbps to 3.3 Gbps operation Dual-loop control of average power and extinction ratio

Contextual Info: ONET1101L w w w .t i.c om SLLS883 – MARCH 2008 11.3 Gbps Laser Diode Driver FEATURES 1 • • • • • • • • • • Up to 11.3 Gbps Operation Two-Wire Digital Interface Digitally Selectable Modulation Current up to 80 mA Digitally Selectable Bias Current up to 100 mA

223878615649

Contextual Info: 11.3 Gbps Active Back-Termination, Differential Laser Diode Driver ADN2526 FEATURES GENERAL DESCRIPTION 3.3 V operation Up to 11.3 Gbps operation Typical 24 ps rise/fall times Full back-termination of output transmission lines Drives TOSAs with resistances ranging from 5 Ω to 50 Ω