I7777 Search Results

T80023

Contextual Info: jl L PRO D UCT NO. 95547- 41.91±0.1 i'} - i a — ^>1 VS/777777;J//J77/7JS7/?7//77777Tr/77/i7777T7% A B O V E P .C .B . RIG H T P U S H ROD TT 5 111 IHI- DIM.S HE- B E L O W P .C .B . L E F T P U S H ROD mot’ l code rev. A 8 C toterance unless otherwise specified

tmp90c84

Contextual Info: TOSHIBA TMP90PH48 CMOS 8-BIT MICROCONTROLLERS TMP90PH48F 1. OUTLINE AND CHARACTERISTICS The TMP90PH48 is a system evalution LSI having a built in One-Time PROM for TMP90C848. A programming and verification for the internal PROM is achieved by using a general EPROM programmer with an adapter socket.

Contextual Info: 16Mbit Synchronous DRAM Series ♦HYUNDAI HY57V164010- 4Mx4bit Synchronous DRAM HY57V168010- 2Mx8blt Synchronous DRAM HY57V161610- 1Mx16bit Synchronous DRAM DESCRIPTION The HY57V164010, HY57V168010, HY57V161610 Programmable options include the length of are high speed 3.3 Volt synchronous dynamic RAMs

Contextual Info: HIIICRTRLYST Umili S E M I C O N D U C T O R CAT64LC10/20/40 1K/2K/4K-Bit Serial E2PROM FEATURES • SPI Bus Compatible Commercial and Industrial Temperature Ranges ■ Low Power CMOS Technology Power-Up Inadvertant W rite Protection ■ 2.5V to 6.0V Operation

Contextual Info: HM6216255HI Series 4M high Speed SRAM 256-kword x 16-bit HITACHI ADE-203-1037A (Z) Rev. 1.0 Apr. 15, 1999 Description The HM6216255HI Series is a 4-M bit high speed static RAM organized 256-k word x 16-bit. It has realized high speed access time by employing CMOS process (4-transistor + 2-poly resistor memory cell) and high

sine wave generation using pcm codec 1110 with ds

Abstract: 04728
Contextual Info: • DESCRIPTION The FUJITSU MB86434 is an AIU audio interface unit LSI for +5 V single-power source digital telephone devices, manufactured using CMOS process technology. The codec transmission filter characteristics meet G.712 standards, and can handle input and output in A-Law, |A-Law and linear conversion modes. The MB86434 also contains the

UPD42S18160G5-70-7-JF

Abstract: UPD42S18160G5707JF uPD42S18160-50 UPD4216160G uPD42S18160G5-50-7JF UPD4216160G5-50 PD42S18160-60 UPD42S18160G5-60-7JF NEC 4216160 UPD4218160G5-80-7JF
Contextual Info: DATA SHEET / MOS INTEGRATED CIRCUIT / PD42S16160,4216160,42S18160,4218160 16 M-BIT DYNAMIC RAM 1 M-WORD BY 16-BIT, FAST PAGE MODE, BYTE READ/WRITE MODE D e s c rip tio n The /xPD42S16160, 4216160, 42S18160, 4218160 are 1,048, 576 words by 16 bits CMOS dynamic RAMs. The

R7F7

Contextual Info: Preliminary H M 5216165 S e r ie s 524,2SS-word x 16-blt x 2-bank Syn ch ro n o u s D ynam ic R A M HITACHI All inpuls and outputs are referred to the rising e d g e o f th e c lo c k in p u t. T h e H M 5 2 1 6 1 6 5 is offered in 2 banks for improved performance.

Contextual Info: M OSEL VITELIC V54C316802VA HIGH PERFORMANCE 3.3 VOLT2M X 8 SYNCHRONOUS DRAM 2 BANKS X 1MBit X 8 CAS Latency = 3 PRELIMINARY 8 10 12 System Frequency fCK 125 MHz 100 MHz 83 MHz Clock Cycle Tim e (tcK 3 ) 8 ns 10 ns 12 ns Clock Access Tim e (tAC3) 7 ns 8 ns

R40 AH

Contextual Info: HM5283206 Series 131,072-word x 32-bit x 2-bank Synchronous Graphic RAM HITACHI ADE-203-223A Z Rev. 1.0 May. 30, 1996 Description All inputs and outputs signals refers to the rising edge of the clock input. The HM5283206 provides 2 banks to realize better performance. 8 column block write function and write per bit function are

UPD4216805L

Contextual Info: NEC MOS INTEGRATED CIRCUIT j u P D 42S 16805L , 4 2 1 6 8 0 5 L 3.3 V OPERATION 16 M BIT DYNAMIC RAM 2 M-WORD BY 8-BIT, HYPER PAGE MODE D escription The //PD42S16805L, 4216805L are 2 097 152 words by 8 bits dynamic CMOS RAMs w ith optional hyper page mode.

MPD424260

Abstract: 424260-70 nec japan
Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT ¿¿PD42S4260, 424260 4 M-BIT DYNAMIC RAM 256 K-WORD BY 16-BIT, FAST PAGE MODE, BYTE READ/WRITE MODE Description The /¿PD42S4260,424260 are 262,144 words by 16 bits dynamic CMOS RAMs. The fast page mode and byte read/write mode capability realize high speed access and low power consumption.

ES-45714-001

Abstract: VERTICAL IC LA 7840 714-3004 ic la 7840
Contextual Info: no te 1 . ; HOUSING M ATL: LCP, U L94V - 0, COLOR B LA C K T E R M IN A L M ATL: CO PPER A L L O Y FINISH: S E L E C T GOLD: 30 N.I. NIN IN CO N TACT A R E A S E L E C T TIN: 150 N.I. NIN IN S O LD E R A R E A O V E R A L L NICKEL U N D E R P L A T E . PRO DUCT SPECIRICATION:

sm 0038 PIN DIAGRAM

Abstract: SMH63VN392M22X40T2 SMH450
Contextual Info: SMH Series a Snap Mount • Large Capacitance ■ High CV ■ High Ripple ■ +85°C Maximum Temperature The SMH series capacitors are the standard 85°C, large capacitance, snap-in capacitors from United Chem-Con. The load life for the SMH series is 2,000 hours at 85°C with the rated ripple current

uPD4265160

Contextual Info: PRELIMINARY DATA SHEET NEC MOS INTEGRATED CIRCUIT ¿¿PD4264160, 4265160 64 M-BIT DYNAMIC RAM 4 M-WORD BY 16-BIT, FAST PAGE MODE D escrip tio n The /iPD4264160,4265160 are 4,194,304 words by 16 bits dynamic CMOS RAMs. The fast page mode capability realize high speed access and low power consumption.

Contextual Info: ADE-203-186A Z i HM5241605 Series 131,072-word x 16-bit x 2-bank Synchronous Dynamic RAM H IT A C H I All inputs and outputs are referred to the rising edge of the clock input. The HMS241605 is offered in 2 banks for improved performance. 3.3 V Power supply

W777777

Contextual Info: JUN 1 2 1992 Ijr‘ VITEUC V52C8128 MULTIPORT VIDEO RAM WITH 128KX8 DRAM AND 256 X 8 SAM HIGH PERFORMANCE V52C8128 80 10 Max. RAS Access Time, tRAc 80 ns 100 ns Max. CAS Access Time, (tcAc) 25 ns 25 ns Max. Column Address Access Time, (t^ ) 45 ns 50 ns Min. Fast Page Mode Cycle Time, (tpc)

Contextual Info: M OSEL VITELIC V54C365164VB HIGH PERFORMANCE 143/133/125 MHz 3.3 V 0 L T 4 M X 16 SYNCHRONOUS DRAM 4 BANKS X 1Mbit X 16 PRELIMINARY 7 75 8PC 8 System Frequency fCK 143 MHz 133 MHz 125 MHz 125 MHz Clock Cycle Tim e (tcK 3 ) 7 ns 7.5 ns 8 ns 8 ns Clock Access Tim e (tAC3) CAS Latency = 3

5380A

Contextual Info: L5380/L53C80 CMOS SCSI Bus Controller FEATURES DESCRIPTION □ Asynchronous Transfer Rrate U p to 4 M bytes/sec □ R n and Functionally Com patible w ith NCR5380, but 2.5x Faster □ Low Pow er C M O S Technology □ On-Chip SC SI Bus D rivers □ Supports A rbitration, Selection/

v52c4258

Contextual Info: M O S E L VTTEUC V52C4258 MULTIPORT VIDEO RAM WITH 256K X 4 DRAM AND 512 X 4 SAM HIGH PERFORMANCE V52C4258 Max. RAS Access Time, I rac 60 70 80 10 60 ns 70 ns 80 ns 100 ns 25 ns Max. CAS Access Time, Ocac ) 15 ns 20 ns 25 ns Max. Column Address Access Time, Paa )

PD42S18160

Abstract: ic321 b4H7525
Contextual Info: DATA SHEET NEC MOS INTEGRATED CIRCUIT /¿ P D 4 2 S 1 8 1 6 0 L , 4 2 1 8 1 6 0 L 3.3 V OPERATION 16 M-BIT DYNAMIC RAM 1 M-WORD BY 16-BIT, FAST PAGE MODE, BYTE READ/WRITE MODE Description The ¿¿PD42S18160L, 4218160L are 1,048,576 words by 16 bits CMOS dynamic RAMs. The fast page mode

Contextual Info: HM5216165 Series 524,288-word x 16-bit x 2-bank Synchronous Dynamic RA M HITACHI ADE-203-280 A (Z) Preliminary Rev. 0.1 Oct. 20,1995 Description A ll inputs and outputs are referred to the rising edge of the clock input. The HM5216165 is offered in 2 banks for improved performance.

HS108

Abstract: HS-108 ltls SI03 SI05 vp77 Mos Electronics
Contextual Info: •% jUK i * ^ VITELIC V52C8126 MULTIPORT VIDEO RAM WITH 128K X 8 DRAM AND 256 X 8 SAM HIGH PERFORMANCE V52C8126 80 10 Max. RAS Access Time, tRAC 80 ns 100 ns Max. CAS Access Time, (tcAC) 25 ns 25 ns Max. Column Address Access Time, (t*) 45 ns 50 ns Min. Fast Page Mode Cycle Time, (tPC)

Contextual Info: NS16C552 National Semiconductor NS16C552 Dual Universal Asynchronous Receiver/Transmitter with FIFOs! General Description Features The NS16C552 is a dual version of the NS16550AF Univer­ sal Asynchronous Receiver/Transmitter UART . The two serial channels are completely independent except for a