HSTL_ Search Results

LA2 DT2

Abstract: BGA64 TC59LM906AMG TC59LM914AMG P-BGA64-1317-1
Contextual Info: TC59LM914/06AMG-37,-50 TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC 512Mbits Network FCRAM1 SSTL_18 / HSTL_Interface − 4,194,304-WORDS x 8 BANKS × 16-BITS − 8,388,608-WORDS × 8 BANKS × 8-BITS DESCRIPTION Network FCRAMTM is Double Data Rate Fast Cycle Random Access Memory. TC59LM914/06AMG is Fast Cycle

Contextual Info: TC59LM914/06AMG-37,-45,-50 TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC 512Mbits Network FCRAM1 SSTL_18 / HSTL_Interface − 4,194,304-WORDS x 8 BANKS × 16-BITS − 8,388,608-WORDS × 8 BANKS × 8-BITS DESCRIPTION Network FCRAMTM is Double Data Rate Fast Cycle Random Access Memory. TC59LM914/06AMG is Fast Cycle

LA2 DT2

Abstract: BGA64 TC59LM906AMG TC59LM914AMG
Contextual Info: TC59LM914/06AMG-37,-50 TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC 512Mbits Network FCRAM1 SSTL_18 / HSTL_Interface − 4,194,304-WORDS x 8 BANKS × 16-BITS − 8,388,608-WORDS × 8 BANKS × 8-BITS DESCRIPTION Network FCRAMTM is Double Data Rate Fast Cycle Random Access Memory. TC59LM914/06AMG is Fast Cycle

Contextual Info: TC59LM914/06AMG-37,-45,-50 TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC 512Mbits Network FCRAM1 SSTL_18 / HSTL_Interface − 4,194,304-WORDS x 8 BANKS × 16-BITS − 8,388,608-WORDS × 8 BANKS × 8-BITS DESCRIPTION Network FCRAMTM is Double Data Rate Fast Cycle Random Access Memory. TC59LM914/06AMG is Fast Cycle

Contextual Info: TC59LM914/06AMG-37,-45,-50 TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC 512Mbits Network FCRAM1 SSTL_18 / HSTL_Interface − 4,194,304-WORDS x 8 BANKS × 16-BITS − 8,388,608-WORDS × 8 BANKS × 8-BITS DESCRIPTION Network FCRAMTM is Double Data Rate Fast Cycle Random Access Memory. TC59LM914/06AMG is Fast Cycle

SY89809L

Contextual Info: 3.3V 1:9 HIGH-PERFORMANCE, LOW-VOLTAGE BUS CLOCK DRIVER Precision Edge SY89809L FEATURES • 3.3V core supply, 1.8V output supply for reduced Precision Edge™ power ■ LVPECL and HSTL inputs DESCRIPTION ■ 9 differential HSTL low-voltage swing output pairs

8B10B

Abstract: C035 CL45 P802 TLK3138
Contextual Info: TLK3138 www.ti.com SLLS762C – FEBRUARY 2007 – REVISED DECEMBER 2009 Dual XAUI Transceiver Check for Samples: TLK3138 • • • • • • • • 1 XGMII Extender Sublayer APPLICATIONS • 10 Gigabit Ethernet Servers and Routers TLK3138 TCLK(0) TD(31.0)

XC3S700A

Abstract: xc3s200aft256 XC3S400AFT256 XC3S50A L01P L02P FG320 UG331 L05P xc3s400a ftg256
Contextual Info: Spartan-3A FPGA Family: Data Sheet R DS529 July 10, 2007 Product Specification Module 1: Introduction and Ordering Information - DS529-1 v1.4.1 July 10, 2007 • • • • • • • Introduction Features Architectural and Configuration Overview General I/O Capabilities

P802

Abstract: TLK3104SA TLK3104SAGNT
Contextual Info: TLK3104SA QUAD 3.125 Gbps SERIAL TRANSCEIVER SCAS651B-− AUGUST 2000 − REVISED SEPTEMBER 2001 D Quad 3.125 Gbps per Channel Transceiver D D D D D D D D Providing 10 Gbps Data Throughput Selectable Synchronized or Independent Channel Operation Selectable Transmitter Only, Receiver Only,

Contextual Info: Artix-7 FPGAs Data Sheet: DC and Switching Characteristics DS181 v1.6 April 17, 2013 Product Specification Introduction Artix -7 FPGAs are available in -3, -2, -1, and -2L speed grades, with -3 having the highest performance. The -2L devices can operate at either of two VCCINT voltages, 0.9V

Contextual Info: Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics DS183 v1.18 November 26, 2013 Product Specification Introduction Virtex -7 T and XT FPGAs are available in -3, -2, -1, and -2L speed grades, with -3 having the highest performance.

EP809

Abstract: MC100EP809 MC100EP809FA MC100EP809FAG MC100 SY89809L MC100EP809FAR2 MC100EP809FAR2G
Contextual Info: MC100EP809 3.3V 1:9 Differential HSTL/PECL to HSTL Clock Driver with LVTTL Clock Select and Enable http://onsemi.com Description The MC100EP809 is a low skew 1−to−9 differential clock driver, designed with clock distribution in mind, accepting two clock sources into

lfxp2-40e

Abstract: LVCMOS25 LD48 LFXP2-17E-5FTN256C HB1004 ispLEVER project Navigator route place LFXP2-5E-5QN IPUG35 LFXP2-8E
Contextual Info: LatticeXP2 Family Handbook HB1004 Version 02.9, May 2011 LatticeXP2 Family Handbook Table of Contents May 2011 Section I. LatticeXP2 Family Data Sheet Introduction Features . 1-1

SPARTAN-3 XC3S400 PQ208

Abstract: SPARTAN-3 XC3S400 pq208 architecture SPARTAN-3 XC3S400 tq144 SPARTAN-3 XC3S400 Spartan-3 FPGA Family XC3S4000-FG676 SPARTAN-3 XC3S400 pin SPARTAN-3 XC3S400 architecture XC3S4000FG676 XILINX SPARTAN VQG100
Contextual Info: 06 Spartan-3 FPGA Family: Introduction and Ordering Information R DS099-1 v1.4 January 17, 2005 Preliminary Product Specification Introduction - The Spartan -3 family of Field-Programmable Gate Arrays is specifically designed to meet the needs of high volume,

XQ4VSX55

Abstract: xq4vlx25 XQ4VLX60-10FF668M XQ4VLX40 XQ4VFX60 xq4vlx60 XQ4VFX60-10EF672M XQ4VLX40-10FF668M XQ4VLX100 Virtex 4Q
Contextual Info: Virtex-4Q FPGA Data Sheet: DC and Switching Characteristics R DS595 v1.6 April 27, 2010 Product Specification Virtex-4Q FPGA Electrical Characteristics Defense-grade Virtex -4Q FPGAs are available in -10 speed grade and are qualified for industrial (TJ = –40°C to +100°C),

XCF00S

Abstract: automotive ecu automotive ecu circuit LVDSEXT-25 AEC-Q100 TS16949 VQG100 LVDSEXT25 BLVDS-25
Contextual Info: 06 Spartan-3 Automotive XA FPGA Family: Introduction and Ordering R DS314-1 v1.0 October 18, 2004 Advance Product Specification Introduction The Xilinx Automotive (XA) Spartan -3 family of Field-Programmable Gate Arrays is specifically designed to meet the

XC3S700AN FGG484

Abstract: XC3S400AN-FGG400 XC3S700A FGG484 xc3s200an XC3S400AN FGG400 FGG676 SPARTAN 3an XC3S50A XC3S700AN-FG484 XC3S700AN
Contextual Info: Spartan-3AN FPGA Family Data Sheet R DS557 June 2, 2008 Module 1: Introduction and Ordering Information - DS557-1 v3.1 June 2, 2008 • • • • • • • • Introduction Features Architectural Overview Configuration Overview In-system Flash Memory Overview

LVDSEXT-25

Abstract: 16x1D LVPECL33 16X1S LVDS-25 LVDS-33 LVDSEXT25 LVDCI18 LVDCI25 LVDS25
Contextual Info: Virtex-II 1.5V Field-Programmable Gate Arrays R DS031-2 v1.9 November 29, 2001 Advance Product Specification Detailed Description Input/Output Blocks (IOBs) Table 1: Supported Single-Ended I/O Standards Virtex-II I/O blocks (IOBs) are provided in groups of two or

EP809

Abstract: MC100EP809 MC100EP809FA MC100EP809FAR2 MC100 SY89809L
Contextual Info: MC100EP809 3.3VĄ1:9 Differential HSTL/PECL to HSTL Clock Driver with LVTTL Clock Select and Enable The MC100EP809 is a low skew 1–to–9 differential clock driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The part is designed for use in low voltage

UG366

Abstract: LX760
Contextual Info: Virtex-6 FPGA Data Sheet: DC and Switching Characteristics DS152 v3.5 May 17, 2013 Product Specification Virtex-6 FPGA Electrical Characteristics Virtex -6 FPGAs are available in -3, -2, -1, and -1L speed grades, with -3 having the highest performance. Virtex-6 FPGA

LFX125B-03F256C

Abstract: LFX1200EB-04F900I pin out lfx1200eb-04f900i LFX1200EB LFX125B-03FN256C LFX125EB-05F256C LFX125B-04F256C LFX125B-05FN256C LFX125B-03F516C LFX500EB
Contextual Info: ispXPGA Device Datasheet June 2010 Select Devices Discontinued! Product Change Notifications PCNs have been issued to discontinue select devices in this data sheet. The original datasheet pages have not been modified and do not reflect those changes. Please refer to the table below for reference PCN and current product status.

lx64ev-3f100c

Abstract: LX64V-3F100C 3F100 5f208c LX64V-3FN100 LX64EB-5F100C LX128EV-5FN208I LX128EV-5FN208C LX64B-3FN100C LX64B-5F100C
Contextual Info: ispGDX2 Device Datasheet June 2010 Select Devices Discontinued! Product Change Notifications PCNs #09-10 has been issued to discontinue select devices in this data sheet. The original datasheet pages have not been modified and do not reflect those changes.

smd 100uf Cha

Abstract: 5304 smd 8 pin ISPPAC-CLK5308S-01TN48I MBR120VLSFT1G RC0805JR-0710KL 100uF CHA ECS-3953M ic 5304 smd 8 pin SMD 100 6n cap DS1010
Contextual Info: ispClock Family Handbook HB1006 Version 01.4, November 2009 ispClock Family Handbook Table of Contents November 2009 Handbook HB1006 Section I. ispClock Family Data Sheets ispClock5600A Family Data Sheet. 1-1

LC4064ZE

Abstract: BSDL Files infineon LFXP6C-3FN256I "x-ray machine" K4H560838E LC4064 LC4256ZE LFXP10C-3F256I LFxP3C-3TN144C PCI x1 express PCB dimensions artwork
Contextual Info: LatticeXP Family Handbook HB1001 Version 03.4, September 2010 LatticeXP Family Handbook Table of Contents September 2010 Section I. LatticeXP Family Data Sheet Introduction Features . 1-1