BLVDS Search Results

Contextual Info: DS92LV1260 DS92LV1260 Six Channel 10 Bit BLVDS Deserializer Literature Number: SNLS134E DS92LV1260 Six Channel 10 Bit BLVDS Deserializer General Description Features The DS92LV1260 integrates six deserializer devices into a single chip. The chip uses a 0.25u CMOS process technology. The DS92LV1260 can simultaneously deserialize up to

DS92LV18

Abstract: 2003120 ds92lv18tvv
Contextual Info: DS92LV18 DS92LV18 18-Bit Bus LVDS Serializer/Deserializer - 15-66 MHz Literature Number: SNLS156D DS92LV18 18-Bit Bus LVDS Serializer/Deserializer - 15-66 MHz General Description Features The DS92LV18 Serializer/Deserializer SERDES pair transparently translates a 18–bit parallel bus into a BLVDS serial

application ds92001

Abstract: DS92001TMA
Contextual Info: DS92001 DS92001 3.3V B/LVDS-BLVDS Buffer Literature Number: SNLS147E DS92001 3.3V B/LVDS-BLVDS Buffer General Description The DS92001 B/LVDS-BLVDS Buffer takes a BLVDS input signal and provides a BLVDS output signal. In many large systems, signals are distributed across backplanes. One of

Contextual Info: DS92LV16 DS92LV16 16-Bit Bus LVDS Serializer/Deserializer - 25 - 80 MHz Literature Number: SNLS138G DS92LV16 16-Bit Bus LVDS Serializer/Deserializer - 25 - 80 MHz General Description Features The DS92LV16 Serializer/Deserializer SERDES pair transparently translates a 16–bit parallel bus into a BLVDS serial

92001

Contextual Info: DS92001 www.ti.com SNLS147F – JUNE 2002 – REVISED APRIL 2013 DS92001 3.3V B/LVDS-BLVDS Buffer Check for Samples: DS92001 FEATURES DESCRIPTION • • The DS92001 B/LVDS-BLVDS Buffer takes a BLVDS input signal and provides a BLVDS output signal. In many large systems, signals are distributed across

Contextual Info: AN 522: Implementing Bus LVDS Interface in Supported Altera Device Families AN-522-2.2 Application Note This application note describes how to implement the Bus LVDS BLVDS interface in the supported Altera device families for high-performance multipoint

Contextual Info: DS92001 3.3V B/LVDS-BLVDS Buffer General Description The DS92001 B/LVDS-BLVDS Buffer takes a BLVDS input signal and provides an BLVDS output signal. In many large systems, signals are distributed across backplanes, and one of the limiting factors for system speed is the "stub length" or

Contextual Info: DS92LV18 DS92LV18 18-Bit Bus LVDS Serializer/Deserializer - 15-66 MHz Literature Number: SNLS156D DS92LV18 18-Bit Bus LVDS Serializer/Deserializer - 15-66 MHz General Description Features The DS92LV18 Serializer/Deserializer SERDES pair transparently translates a 18–bit parallel bus into a BLVDS serial

Contextual Info: 19-2130; Rev 2; 11/10 KIT ATION EVALU ABLE AVAIL 10-Bit Bus LVDS Deserializers The MAX9206/MAX9208 deserializers transform a highspeed serial bus low-voltage differential signaling BLVDS data stream into 10-bit-wide parallel LVCMOS/ LVTTL data and clock. The deserializers pair with serializers such as the MAX9205/MAX9207, which generate a serial BLVDS signal from 10-bit-wide parallel

Contextual Info: DS08MB200 www.ti.com SNLS197C – MAY 2006 – REVISED SEPTEMBER 2012 DS08MB200 Dual 800 Mbps 2:1/1:2 LVDS Mux/Buffer Check for Samples: DS08MB200 FEATURES 1 • • 2 • • Up to 800 Mbps data rate per channel LVDS/BLVDS/CML/LVPECL compatible inputs, LVDS compatible outputs

Contextual Info: DS92001 www.ti.com SNLS147F – JUNE 2002 – REVISED APRIL 2013 DS92001 3.3V B/LVDS-BLVDS Buffer Check for Samples: DS92001 FEATURES DESCRIPTION • • The DS92001 B/LVDS-BLVDS Buffer takes a BLVDS input signal and provides a BLVDS output signal. In many large systems, signals are distributed across

Contextual Info: DS92LV1260 www.ti.com SNLS134F – DECEMBER 2000 – REVISED APRIL 2013 DS92LV1260 Six Channel 10 Bit BLVDS Deserializer Check for Samples: DS92LV1260 FEATURES DESCRIPTION • The DS92LV1260 integrates six deserializer devices into a single chip. The chip uses a 0.25u CMOS

tma price

Contextual Info: DS92001 www.ti.com SNLS147F – JUNE 2002 – REVISED APRIL 2013 DS92001 3.3V B/LVDS-BLVDS Buffer Check for Samples: DS92001 FEATURES DESCRIPTION • • The DS92001 B/LVDS-BLVDS Buffer takes a BLVDS input signal and provides a BLVDS output signal. In many large systems, signals are distributed across

XP170E

Abstract: XP220E XP272E XP378E XP444E XP568E XP708E XP830E 124mA Cell-based ASICs - Reference Library
Contextual Info: XPressArray 0.18µ Hybrid Gate Array 1.0 Key Features • Supports LVTTL, LVCMOS, PCI, PCI-X, HSTL, SSTL, GTL/+, LVPECL, LVDS, BLVDS • 1.5V, 1.8V, 2.5V and 3.3V capable I/O • True 3.3V and 5V tolerance with no external resistor necessary • Up to 830 user I/Os

AN-1217

Abstract: DS92LV16 DS92LV16TVHG VHG80A
Contextual Info: DS92LV16 16-Bit Bus LVDS Serializer/Deserializer - 25 - 80 MHz General Description Features The DS92LV16 Serializer/Deserializer SERDES pair transparently translates a 16–bit parallel bus into a BLVDS serial stream with embedded clock information. This single serial

Contextual Info: DS92LV1260 www.ti.com SNLS134F – DECEMBER 2000 – REVISED APRIL 2013 DS92LV1260 Six Channel 10 Bit BLVDS Deserializer Check for Samples: DS92LV1260 FEATURES DESCRIPTION • The DS92LV1260 integrates six deserializer devices into a single chip. The chip uses a 0.25u CMOS

DS92CK16

Abstract: DS92CK16TMTC MTC24 DS101082
Contextual Info: DS92CK16 3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver General Description Features The DS92CK16 1 to 6 Clock Buffer/Bus Transceiver is a one to six CMOS differential clock distribution device utilizing Bus Low Voltage Differential Signaling BLVDS technology. This

DS92LV18

Contextual Info: DS92LV18 18-Bit Bus LVDS Serializer/Deserializer - 15-66 MHz General Description Features The DS92LV18 Serializer/Deserializer SERDES pair transparently translates a 18–bit parallel bus into a BLVDS serial stream with embedded clock information. This single serial

DS92001TLD

Abstract: DS92001TM M08A DS92001
Contextual Info: DS92001 3.3V B/LVDS-BLVDS Buffer General Description The DS92001 B/LVDS-BLVDS Buffer takes a BLVDS input signal and provides an BLVDS output signal. In many large systems, signals are distributed across backplanes, and one of the limiting factors for system speed is the ’stub length’ or

Contextual Info: DS92CK16 www.ti.com SNAS044B – MAY 2004 – REVISED APRIL 2006 DS92CK16 3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver Check for Samples: DS92CK16 FEATURES 1 • 23 • • • • • Master/Slave clock selection in a backplane application 125 MHz operation typical

DS92LV1021

Abstract: DS92LV1210 DS92LV1212
Contextual Info: Using the BLVDS02 Demo Kit The BLVDS02 Demo Kit was designed to allow the user to observe the operation of the DS92LV1021 Serializer and the DS92LV1212 Deserializer. Several configurations are possible. With the purchase of additional kits, multi-drop applications can be modeled.

AN805

Abstract: AN807 AN905 AN916 DS92CK16 DS92CK16TMTC MTC24
Contextual Info: DS92CK16 3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver General Description Features The DS92CK16 1 to 6 Clock Buffer/Bus Transceiver is a one to six CMOS differential clock distribution device utilizing Bus Low Voltage Differential Signaling BLVDS technology. This

glossary

Abstract: Emitter Coupled Logic TRANSISTOR RADIO RECEIVER radio and electromagnetic interference National Standards Institute
Contextual Info: Glossary, Index and Worldwide Sales Offices Appendix GLOSSARY AN Application Note ANSI American National Standards Institute ASIC Application Specific Integrated Circuit B/P Backplane BER Bit Error Rate BERT Bit Error Rate Test BLVDS Bus LVDS BTL Backplane Transceiver Logic

SCAN921023

Abstract: SCAN921260 UJB196A deserializer LVDS Serializer
Contextual Info: SCAN921260 x6 1:10 BLVDS Deserializer with IEEE 1149.1 and At-speed BIST Test Modes Product Brief DIN6± TDI TDO TMS 5/ TCK TRST BSR BSR BSR BSR BSR BSR BSR Output Registers MUX BSR BSR BSR DIN5± Deserialize & BIST DIN4± BSR DIN3± BSR DIN2± BSR DIN1±