LVDS33 Search Results

ECS-LVDS33

Abstract: LVDS-25 LVDS25 LVDS-33
Contextual Info: ECS-LVDS25/LVDS33 SMD CLOCK OSCILLATOR The ECS-LVDS25 2.5V and LVDS33 (3.3V) Low Voltage Differential Signaling Oscillators. The miniature, very low profile leadless ceramic package is ideal for today's SMD manufacturing environment. Fixed LVDS Model

ECS-LVDS25/LVDS33 LVDS

Abstract: Oscillators LVDS33 LVDS-33 LVDS footprint ECS-LVDS25-1000-A LVDS-25
Contextual Info: ECS-LVDS25/LVDS33 LVDS 7 x 5 mm Footprint Low Jitter Pb Free/RoHS Compliant SMD LVDS OSCILLATOR ECS-LVDS25 2.5V and ECS-LVDS33 (3.3V) Low Voltage Differential Signaling SMD LVDS oscillators. OPERATING CONDITIONS / ELECTRICAL CHARACTERISTICS PARAMETERS CONDITIONS

ECS-LVDS25-1000-A

Contextual Info: ECS-LV DS2 5 /LV DS3 3 LVDS 7 x 5 mm Footprint Low Jitter Pb Free/RoHS Compliant SM D LV DS OSCI LLAT OR ECS-LVDS25 2.5V and ECS-LVDS33 (3.3V) Low Voltage Differential Signaling SMD LVDS oscillators. OPERATING CONDITIONS / ELECTRICAL CHARACTERISTICS PARAMETERS

LCMXO2-1200HC-4TG100C

Abstract: LCMXO2-256HC-4TG100I LCMXO2-1200 tn1200 lcmxo2 LCMXO2-1200HC-4TG100 LCMXO2-2000 LCMXO2-7000 MachXO2-1200 LCMXO2-4000HC
Contextual Info: MachXO2 Family Handbook HB1010 Version 01.0, November 2010 MachXO2 Family Handbook Table of Contents November 2010 Section I. MachXO2 Family Data Sheet Introduction Features . 1-1

smd 100uf Cha

Abstract: 5304 smd 8 pin ISPPAC-CLK5308S-01TN48I MBR120VLSFT1G RC0805JR-0710KL 100uF CHA ECS-3953M ic 5304 smd 8 pin SMD 100 6n cap DS1010
Contextual Info: ispClock Family Handbook HB1006 Version 01.4, November 2009 ispClock Family Handbook Table of Contents November 2009 Handbook HB1006 Section I. ispClock Family Data Sheets ispClock5600A Family Data Sheet. 1-1

BLVDS-25

Abstract: LVDSEXT-25 4564 RAM XC2VP70 FF1704 pinout XC2V1000 Pin-out XC2V1500 XC2V2000 XC2V3000 XC2V6000 XC2V8000
Contextual Info: Xilinx Virtex-II Series FPGAs and RocketPHY Physical Layer Transceivers Transceiver Blocks 992 88 120 200 264 432 528 624 720 912 1104 1108 Chip Scale Packages CS – wire-bond chip-scale BGA (0.8 mm ball spacing) 144 8 88 92 FF896 92 8 FF1152 BGA Packages (BG) – wire-bond standard BGA (1.27 mm ball spacing)

EP2C5

Abstract: F256 LVDS11P LVDS20P a5201
Contextual Info: Pin Information for the Cyclone II EP2C5 Device Version 1.9 Note 1 , (2) Bank Number VREFB Group Pin Name / Function Optional Function(s) Configuration T144 Q208 F256 DQS for x8/x9 in Function T144 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1

EP2C20

Abstract: DDR2 pin out EP2C15A F256 EP2C20A
Contextual Info: Cyclone II EP2C15A, EP2C20 & EP2C20A Device Pin-Out PT-EP2C20-2.1 2008 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are

lvdt

Abstract: AM26LS32 SN65LVDS32B SN65LVDS33 SN65LVDS33D SN65LVDS34 SN65LVDS9637B SN65LVDT33 SN65LVDT34
Contextual Info: LVDS33, SN65LVDT33, SN65LVDS34, SN65LVDT34 HIGH-SPEED DIFFERENTIAL RECEIVERS SLLS490A – MARCH 2001 – REVISED MAY 2001 D D D D D D D D D D D D 400-Mbps Signaling Rate1 and 200-Mxfr/s Data Transfer Rate Operates With a Single 3.3-V Supply –4-V to 5-V Common-Mode Input Voltage

Contextual Info: LVDS33, SN65LVDT33, SN65LVDS34, SN65LVDT34 HIGHĆSPEED DIFFERENTIAL RECEIVERS SLLS490B − MARCH 2001 − REVISED NOVEMBER 2004 D 400-Mbps Signaling Rate1 and 200-Mxfr/s D D D D D D D D D D D Data Transfer Rate Operates With a Single 3.3-V Supply −4-V to 5-V Common-Mode Input Voltage

MAX3234

Abstract: maxim dallas 2501 jtag gd75232 DALLAS 2501 jtag PL-2303 LGA 775 SOCKET PIN LAYOUT SN75176 PL-2303 SN75179 application MAX490 schematic
Contextual Info: R E A L W O R L D S I G N A L P TM R O C E S S I N G Interface Selection Guide 2Q 2004 Table of Contents Introduction .3 Data Line Circuits High-Speed Interconnect LVDS, xECL, CML .4

XQR2V3000-4CG717V

Abstract: XQR2V1000-4BG575R XQR2V6000-4CF1144H XQR2V3000-4CG717M XQR2V1000-4BG575N AH165 CG717 XQR2V3000-4BG728R XQR2V1000-4FG456R XQR2V6000
Contextual Info: R < B L QPro Virtex-II 1.5V Radiation-Hardened QML Platform FPGAs DS124 v1.2 December 4, 2006 Product Specification Summary of Radiation Hardened QPro Virtex-II Features • • • • • • • • • • • • • Industry First Radiation Hardened Platform FPGA

Contextual Info: LVDS33, SN65LVDT33, SN65LVDS34, SN65LVDT34 HIGHĆSPEED DIFFERENTIAL RECEIVERS SLLS490B − MARCH 2001 − REVISED NOVEMBER 2004 D 400-Mbps Signaling Rate1 and 200-Mxfr/s D D D D D D D D D D D Data Transfer Rate Operates With a Single 3.3-V Supply −4-V to 5-V Common-Mode Input Voltage

AM26LS32

Abstract: SLLS490B SN65LVDS32B SN65LVDS33 SN65LVDS34 SN65LVDS9637B SN65LVDT33 SN65LVDT34 SN65LVDS LVDT aerospace
Contextual Info: LVDS33, SN65LVDT33 SN65LVDS34, SN65LVDT34 www.ti.com SLLS490B – MARCH 2001 – REVISED NOVEMBER 2004 HIGH-SPEED DIFFERENTIAL RECEIVERS FEATURES • • • • • • • • • • • • 1 400-Mbps Signaling Rate(1) and 200-Mxfr/s Data Transfer Rate

diode B4 discription

Abstract: DDR2 pin out F256
Contextual Info: Cyclone II EP2C8 & EP2C8A Device Pin-Out PT-EP2C8-1.9 2008 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or

lvds125

Abstract: F324 F400
Contextual Info: Pin Information for the Cyclone EP1C4 Device Version 1.3 Bank Number VREFB Group Pin Name / Function B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 VREF0B1 VREF0B1 VREF0B1

UG381

Abstract: hitachi sr 2010 receiver oserdes2 DDR spartan6 HDMI verilog code ISERDES2 JESD79-3 XC6SLX Spartan-6 LX45 XC6slx45 xc6slx75
Contextual Info: Spartan-6 FPGA SelectIO Resources User Guide UG381 v1.4 December 16, 2010 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the

SN65LVDS100 Application Report

Abstract: CDC111 CDCLVP110 CDCVF111 SN65LVDS101 SN65LVDT100 SN65LVDT33 SLLA101 sn65lvds CML100
Contextual Info: Application Report SCAA059C – March 2003 – Revised October 2007 AC-Coupling Between Differential LVPECL, LVDS, HSTL, and CML Kal Mustafa/Chris Sterzik. High Performance Analog

Contextual Info: MachXO2 Family Data Sheet DS1035 Version 2.6, July 2014 MachXO2 Family Data Sheet Introduction February 2014 Features Data Sheet DS1035  Flexible On-Chip Clocking • Eight primary clocks • Up to two edge clocks for high-speed I/O  interfaces top and bottom sides only

M2GL005

Abstract: db hpms
Contextual Info: Revision 0 IGLOO2 FPGAs Introduction Microsemi’s IGLOO 2 FPGAs integrate fourth generation flash-based FPGA fabric and high performance communications interfaces on a single chip. The IGLOO2 family is the industry’s lowest power, most reliable, and the most secure programmable logic solution. This next generation IGLOO2

DS1047

Contextual Info: MachXO3L Family Data Sheet Advance DS1047 Version 00.2, February 2014 MachXO3L Family Data Sheet Introduction February 2014 Advance Data Sheet DS1047 Features  Solutions • • • • • • • • • • Smallest footprint, lowest power, high data

lvds34

Abstract: SLLA033
Contextual Info: LVDS33, SN65LVDT33 SN65LVDS34, SN65LVDT34 www.ti.com SLLS490B – MARCH 2001 – REVISED NOVEMBER 2004 HIGH-SPEED DIFFERENTIAL RECEIVERS FEATURES • • • • • • • • • • • • 1 400-Mbps Signaling Rate(1) and 200-Mxfr/s Data Transfer Rate

XP170E

Abstract: XP220E XP272E XP378E XP444E XP568E XP708E XP830E 124mA Cell-based ASICs - Reference Library
Contextual Info: XPressArray 0.18µ Hybrid Gate Array 1.0 Key Features • Supports LVTTL, LVCMOS, PCI, PCI-X, HSTL, SSTL, GTL/+, LVPECL, LVDS, BLVDS • 1.5V, 1.8V, 2.5V and 3.3V capable I/O • True 3.3V and 5V tolerance with no external resistor necessary • Up to 830 user I/Os

XQ2V1000-4FG456N

Abstract: XQ2V1000 Virtex Qpro xq2v1000-4bg575n CG717 CF1144 matrix m21 vhdl code for carry select adder using ROM XQ2V1000-4BG XQ2V3000
Contextual Info: ds122_1_1.fm Page 1 Wednesday, January 7, 2004 9:15 PM QPro Virtex-II 1.5V Military QML Platform FPGAs R DS122 v1.1 January 7, 2004 Product Specification Summary of QPro Virtex™-II Features • • • • • • • • Industry First Military Grade Platform FPGA Solution