H256 Search Results

Contextual Info: M H25609ATN-10 2359296-BIT 262144-WORD BY 9-BITJCMOS STATIC RAM DESCRIPTION The M H 25609ATN m o du le organized is a 2 3 5 9 2 9 6 - b it CMOS s ta tic as 2 6 2 1 4 4 - w o rd o f tw o in d u s try s ta n d a rd 128K x8 R AM PIN CONFIGURATION (TOP VIEW [Single side]

MH25632CNXJ-7

Contextual Info: MITSUBISHI LSIs DRAM MODULE H25632CNXJ-6,-7 FAST PAGE MODE 83886Q8-BIT(262144-WORD BY 32-BIT)DYNAMIC RAM DESCRIPTION PIN CONFIGURATION (TOP VIEW) [Single side] The M H25632CN XJ is 262144-word by 32-bit dynamic RAM module. That module consists of two industry 256K

m5m44256

Contextual Info: MITSUBISHI LSIs H25616PNA-10,-12 4 1 9 4 3 0 4 -B IT 2 6 2 1 4 4 -WORD BY 16-BIT PSEUDO-PSEUDO STATIC RAM MODULE DESCRIPTION The M H25616PNA ¡5 262144 word x 16 bit PSEUDOPSEUDO static RAM and consist of four industry standard 256K x 4 bit dynamic RAMs in SOJr two data selector in

MH25609AJ-85

Contextual Info: M IT S U B IS H I LSIs H25609AJ-85, -10,-12/ H25609AJ A-85,-10,-12 M O D E 2 6 2 1 4 4 -W O R D B Y 9 - B IT D Y N A M IC R A M DESCRIPTIO N PIN C O N F IG U R A T IO N TOP VIE W The M H25609AJ, AJA is 262144 word x 9 bit dynamic RAM and consists of two industry standard 256K x 4

44256 ram

Contextual Info: MITSUBISHI LSIs H25616PNA-10,-12 4 1 9 4 3 0 4 -B IT 2 6 2 1 4 4 -W 0 R D BY 16-BIT PSEUDO-PSEUDO STATIC RAM DESCRIPTIO N The PIN C O N F IG U R A T IO N (TOP V IE W ) M H25616PN A is 2 6 2 1 4 4 w o rd x 16 b it PSEUDO- P S E U D O s ta tic R A M a n d c o n s is t o f f o u r in d u s tr y s ta n d a rd

Contextual Info: ç ,V M ITSUBISHI LS Is H25616RNA, •15, -2 ? > - ! .’ * ' ' ' 4 1 9 4 3 0 4 - B I T 2 6 2 1 4 4 -WORD B Y 16-B IT CMOS E R A S A B LE AND E L E C T R IC A L L Y REPROGRAM M ABLE ROM DESCRIPTIO N ^ The M H25616RNA is 262144-word x 16-bit EPROM and consists of four industry standard 128K x 8 EPROMs and

M5M5256

Contextual Info: MITSUBISHI LSIs M H2S609SN-10 2 3 5 9 2 9 6 - B I T 2 6 2 1 4 4 -WORD BY 9 -B IT CMOS STATIC RAM DESCRIPTION The M H25609SN is a 2 3 5 6 2 9 6 -b it CMOS s ta t ic RAM PIN CONFIGURATION (TOP VIEW) m o d u le o r g a n iz e d as 2 6 2 1 4 4 - w o r d b y 9 - b its . I t co n sists o f

sam3-h256

Abstract: olimex
Contextual Info: SAM3-H256 development board Users Manual All boards produced by Olimex are ROHS compliant Rev. Initial, April 2011 Copyright c 2011, OLIMEX Ltd, All rights reserved Page 1 INTRODUCTION: Atmel’s ATSAM3S4BA-AU is a member of a series of Flash microcontrollers based on the high performance 32-bit ARM Cortex-M3 RISC processor. It operates at a maximum speed of 64 MHz and features a 256 Kbyte Flash and a 48 Kbyte

44256BJ

Contextual Info: M ITSUBISHI L S Is M H25636BJ-85, -10, -12 9 4 3 7 1 8 4 -B IT 2 6 2 144-W ORD BY 36-B IT D Y N A M IC RAM DESCRIPTION The M H 25 636 B J is 26 2,14 4-w o rd x 3 6 bit dynam ic R A M . PIN CONFIGURATION (TOP VIEW) This consists o f fo u r industry standard 2 5 6 K x 1 dynamic

Contextual Info: M ITSUBISHI LSIs M H25636AJ-85, -10, -12 9 4 3 7 1 8 4 -B IT 2 6 2 144-W ORD BY 3 6 -B IT D Y N A M IC RAM DESCRIPTION The M H 2 5 6 3 6 A J is 26 2,14 4-w o rd x 3 6 bit dynam ic R A M . PIN CONFIGURATION (TOP VIEW) This consists o f fo u r industry standard 2 5 6 K x 1 dynam ic

MH25609-10

Abstract: M5M4256 tfk 540
Contextual Info: M ITSUBISHI L S Is H25609J-85,-10,-12,-15/ H25609JA-85,-10,-12,-15 PA G E MODE 2 6 2 1 4 4 - WORD B Y 9 -B IT DYNAMIC RAM DESCRIPTION The M H25609J, JA is 262144 w ord x 9 b it dynam ic RAM and consists o f nine industry standard 256K x 1 dynamic PIN CONFIGURATION TOP VIEW

Contextual Info: M IT S U B IS H I LSIs g f l| P M H25609AJ-85,-10, -12/ H25609AJ A-85, -10,-12 PA G E M O D E 2 6 2 1 4 4 - W O R D B Y 9 - B IT D Y N A M IC R A M DESCRIPTION The M H 2 5 6 0 9 A J , A JA is 2 6 2 1 4 4 word x 9 b it dynam ic R A M and consists o f tw o industry standard 2 5 6 K x 4

Contextual Info: AT91SAM7S256 HEADER DEVELOPMENT PROTOTYPE BOARD SAM7-H256 HEADER DEVELOPMENT BOARD FOR AT91SAM7S256 ARM7TDMI-S MICROCONTROLLER 11:05:06 AM] AT91SAM7S256 HEADER DEVELOPMENT PROTOTYPE BOARD FEATURES: MCU: AT91SAM7S256 16/32 bit ARM7TDMI with 256K Bytes Program Flash, 64K

Contextual Info: GEC PLESSEY ADVANCE INFORMATION 3060-2 1 SP4660 1GHz-t-256 PRESCALER WITH LOW CURRENT AND LOW RADIATION The SP4660 h-256 prescaler is one of GPS’ range of high speed dividers for consum er frequency synthesis and measurement systems. It has a low supply current, giving reduced

Contextual Info: Order this data sheet by MCA2200ECL/D M O TO RO LA MCA2200ECL 1 SEMICONDUCTOR TECHNICAL DATA MCA2200ECL MACROCELL ARRAY The MCA2200ECL Array is a m em ber of M otorola's "T h ird G eneration” MCA3 ECL series. M otorola's MOSAIC III process provides the MCA2200ECL w ith the logic pow er of over 2200

25608

Abstract: M5M5256 MH25608TNA-10H
Contextual Info: MITSUBISHI LSIs H25608TNA-85L,-10L,-12L,-15L/ H25608TNA-85H,-10H,-12H,-15H 2 0 9 7 1 5 2 -B IT 2 6 2 144-WORD BY 8-BIT CM 0S STATIC RAM DESCRIPTION PIN CONFIGURATION (TOP VIEW) The M H 2 5 6 0 8 T N A is a 2 0 9 7 1 5 2 bits CMOS static R A M module organized as 26 2144 -w o rd s by 8-bits. It consists

25608

Contextual Info: MITSUBISHI LSIs H25608AJ-8,-10, -12/ H25608AJA-8, -10, •12 FAST P A G E MODE 262144-W ORD BY 8-BIT DYNAMIC RAM DESC RIPTIO N The H25608AJ, A JA is 262144 word x 8 bit dynamic RAM and consists of two industry standard 256K x 4 dynamic RAMs in SO J. The mounting of SO J on a single in-line package pro­

Contextual Info: MITSUBISHI cC O N T R O L/ DRIVER IC> M54975P/FP Bi-CMOS 8-BIT SERIAL-INPUT LATCHED DRIVER D E S C R IP T IO N P IN C O N F IG U R A T I O N T O P V IE W The M 54975 is a sem iconductor integrated circuit fabricated using Bi-CM O S technology. It contains a serial input to serial/parallel

Contextual Info: m i c r o e l e c t r o n i c s group Preliminary Data Sheet December 1997 Lucent Technologies Bell Labs Innovations TEC03264 32-Channel Echo Canceler Features Applications Overall Device • Digital terrestrial communication networks ■ Dual-convergence voice band echo canceler

5252 F

Abstract: "5252 F" THR15 H-38-9 SVTD "switching office" svts 052 Motorola 0X69 TEC032642 ATM H008
Contextual Info: Data Sheet August 1999 microelectronics group Lucent Technologies Bell Labs Innovations TEC03264 32-Channel Echo Canceller Features Applications Overall Device • ■ ■ ■ ■ Dual-convergence voiceband echo canceller EC . ■ 32 independent and individually controlled echo

m5m4256

Abstract: MH25608-15 30N9 MH25608J12 MH25608-12 MH25608J-12 MH25608J-10 MH25608J-85 MH25608JA-10 MH25608JA-85
Contextual Info: MITSUBISHI LSIs H25608J-85,-10,-12,-15/ H25608JA-85,-10,-12,-15 PAGE M ODE 2 6 2 1 4 4 - WORD BY 8 -B IT D Y N A M IC RAM DESCRIPTION The H25608J, JA is 262144 word x 8 bit dynamic RAM and consists of nine industry standard 256K x 1 dynamic RAMs in plastic leaded chip carrier.

MH25608S1N-15

Abstract: MH25608S1N-70 MH25608S1N-10 2097152-BIT
Contextual Info: M IT S U B IS H I LS Is H25608S1N-70, -85, -10, -12,-iS 2 0 9 7 1 5 2 - B I T 2 6 2 1 4 4 - W 0 R D BY 8 -B IT C M O S STATIC RAM MODULE DESCRIPTION The M H 25 608 S 1 N is a 2 0 9 7 1 5 2 bits CMOS static R A M PIN CONFIGURATION (TOP VIEW) module organized as 26 2144 -w o rd s by 8-bits, it consists

NC26S

Abstract: MH25608AJ-8 MH25608AJA-8 MA2560
Contextual Info: M IT S U B IS H I LSIs H25608AJ-8,-10,-12/ H25608AJ A-8, -10,-12 OE MODE 2 6 2 1 4 4 -WORD BY S -B IT DYNAM IC RAM DESCRIPTIO N The M H 2 5 6 0 8 A J , A JA is 2 6 2 1 4 4 w ord x 8 bit dynam ic R A M and consists of tw o industry standard 2 5 6 K x 4 dynam ic RAMs in SOJ.

H331 transistor

Abstract: transistor h331 ZX-03 10000 series of ECL gates H375 L892 MCA2500ECL Nippon capacitors l421 L817
Contextual Info: Order this data sheet by MCA10000ECL/D M O TO RO LA SEM ICO NDUCTO R TECHNICAL DATA M C A 10000E C L M ACROCELL ARRAY MCA3 ECL SERIES The MCA10000ECL A rra y is a m e m b e r o f M o to ro la 's "T h ird G e n e ra tio n " MCA3 ECL series. M o to ro la 's MOSAIC III process