FPWL Search Results

82C54-2-P

Contextual Info: 47E » m Ö235b05 0G321flfl S • SIEG SIEMENS AKTIENGESELLSCHAF Av* "T-S W ^ y $ t\ SAB 82C54 Programmable CMOS Interval Timer SAB 82C54 up to 8 MHz SAB 82C54-2 up to 10 MHz • C om patible w ith all Siemens and m ost other microprocessors • Six program m able counter modes

Contextual Info: L3M Device Level 3 Mapper TXC-03452B DATASHEET FEATURES DESCRIPTION = The L3M maps a DS3 line signal into an STM-1 TUG-3 or STS-3/STS-1 SPE or STS-1 SPE SDH/SONET sig­ nal. An E3 line signal is mapped into an STM-1 TUG-3 signal only. The L3M provides a TUG-3 formatted signal

Contextual Info: SANYO SEMICONDUCTOR CORP SSE D 7 ^ 7 0 7 ^ 0007107 T -3 2SC4519 1 5 - I S . # 2018A N P N Epitaxial P la n a r S ilic o n T ran sis to r High-Speed Switching Applications 3133 Features . Adoption of FBET process • Low collector-to-emitter saturation voltage

Contextual Info: C ir - S A V « J IU SP 1072 V .Ä Cotpcxa'ioo“ SIGNAL PROCESSING EXCELLENCE DUAL CHANNEL 8-BIT 25 MSPS A /D CONVERTER FEATURES • Two 8-Bit 25 MHz Flash A/Ds in a Single Package ■ Separate Input Buffer Amplifier and High Speed Limiter for Each Channel

M51308SP

Abstract: m51346ap M51390ASP m51412sp M51346 PAL 007 A m51308 NOTES M51390 m51412
Contextual Info: M ITSU BISHI ICS A V CO M M O N M51390ASP PAL/NTSC VIDEO CH R O M A DEFLECTIO N DESCRIPTION PIN CONFIGURATION (TOP VIEW) The M51390ASP is a semiconductor integrated circuit for video, chroma, and deflection. Combined with IC M51346AP B-Y OUT d R-Y OUT E

82c53

Abstract: 82c53-5
Contextual Info: 47E SIEMENS D • 053SbDS GG321b4 AKTIENGESELLSCHAF b M SIEG T 5 H ^ \ SAB 82C53 Programmable CMOS Interval Timer S A B 82C53: Com m and W idth 400 ns S A B 82C53-5: Com m and Width 300 ns • Compatible with all S iem e n s and m ost other m icroprocessors

CH341A

Abstract: digital trainer schematic diagram laf 0001 CH3401 J0123 ccs ldl HP 3D6 000A75 X77H-X70H TO SI 788 48D
Contextual Info: H i/1 I - = - ^ • QE1F Device Quad E1 Framer TXC-03104 DATA SHEET FEATURES DESCRIPTION • Offline framer supports Standard and Frame Hold-Off frame alignment with CRC-4 multiframe check and selectable out of frame criteria, and

Contextual Info: E2/E3F Device 8-, 34 Mbit/s Framer TXC-03701 v DATA SHEET W FEATURES DESCRIPTION Framer for CCITT Recommendations: - G.742 8448 kbit/s - G.745 (8448 kbit/s) - G.751 (34368 kbit/s) - G.753 (34368 kbit/s) = The E2/E3 Framer (E2/E3F) is a CMOS VLSI device that provides the functions needed to frame a wideband

RD4A

Contextual Info: XBERT Device Bit Error Rate Generator Receiver TXC-06125 DATA SHEET Preliminary FEATURES = — — — - = • Serial, nibble, or byte wide interface capability • Transmit and receive clock rate: 100 Hz to 52.00 MHz serial, byte, nibble I/O (All telecom rates

RP02

Contextual Info: QT1M Device Quad T1 Mapper TXC-04251 DATA SH EE T Product Preview FEATURES DESCRIPTION The Quad T1 Mapper device is designed for add/drop multiplexer, terminal multiplexer, and dual and single unidirectional ring applications. Four T1 1.544 Mbit/s signals are mapped to and from asynchronous 1.5 Vir­

Contextual Info: MP8782 CMOS 5 MSPS, 10-Bit High Speed Analog-to-Digital Converter FEATURES APPLICATIONS • • • • • « 10-Bit Resolution 5 MHz Sampling Rate DNL = ±1 LSB, INL = ±2 LSB Internal S/H Function Single 5 V Power Supply V!N DC Range: 0 V to VDD VREp DC Range: 1 V to VDD

Contextual Info: & I S P S T P T 7 9 2 12-BIT, 10 MSPS, TTL, A/D CONVERTER SIGNAL PROCESSING TECHNOLOGIES FEATURES APPLICATIONS • • • • • • • • • • • • • • • • Monolithic 12-Bit 10 MSPS Converter 66 dB SNR @ 1 MHz Input On-Chip Track/Hold Bipolar ±2.0 V Analog Input

fpwl2110

Abstract: FPWL MKT-DS-ETEK-0001 uniphase fpwl Fabry-Perot 1550 nm Etalon pin photodiode 10 ghz etalon locker fpwl21150 lucent wdm
Contextual Info: Product Bulletin Fabry-Perot WavelockerTM The Fabry-Perot WavelockerTM is a thermally stable etalon-based device used to stabilize laser sources for high-density WDM applications. With both 50 and 100 GHz designs, the WavelockerTM can stabilize any channel on the 100 GHz ITU grid

Contextual Info: COBRA Device Constant Bit Rate ATM Adaptation Layer 1 TXC-05427B DATASHEET DESCRIPTION = = COBRA Constant Bit Rate ATM Adaptation Layer 1 is a four-channel VLSI device that implements all of the functions needed for circuit emulation over ATM. Both Unstructured service (e.g., 1544 kbit/s and 2048 kbit/s)

Contextual Info: MP87L82 Low V oltage C M O S 10-B it 2 M H z A nalog-to-D igital C o n verter JU k Micro Power Systems FEATURES APPLICATIONS • • • • • • • • • • • • • • • • • • • • • • • • 3.3 V Operation 10-Bit Resolution 2 MHz Sampling Rate

Contextual Info: SAB 82C54 Programmable CMOS Interval Timer SAB 82C54 up to 8 MHz SAB 82C54-2 up to 10 MHz • Compatible with all Siem ens and most other microprocessors • Three independent 16-bit counters • Handles inputs from DC to 8 MHz 10 MHz for SAB 82C54-2 • Low power CMOS

514256BZ-70

Abstract: 514256BJ-70 514256 CCC-13 514256b-70 514256b-60 BL6040
Contextual Info: SIE M E N S 256 K X 4 -B it D ynam ic RAM Low Pow er 256 K x 4-B it D ynam ic RAM HYB 514256B/BJ/BZ-60/-70/-80 HYB 514256BU B JL/BZL-60/-70 Advanced Information • • 262 144 words by 4-bit organization Fast access and cycle time 60 ns access time 110 ns cycle tim e HYB 514256B/BL-60

75C48

Abstract: IDT75C48 o1111111
Contextual Info: 14E D INTEGRATED DEVICE 4A25771 0 D 0 4 2 7 ci 7 CMOS FLASH A/D CONVERTER IDT 75C48 FEATURES: DESCRIPTION: • 8-bit resolution Th e IDT75C48 is a 30 M egaSam ple per Second M SPS , fully parallel, 8-bit Flash Analog to Digital Converter. The wide input analog bandwidth of 10 MHz permits the conversion of analog in­

XCKJ

Abstract: XCK-L txc 7a XCK-L option Digital Alarm Clock by ttl LIMING RELAY LIMING VOLTAGE RELAY n191 TXC-02050 F1785
Contextual Info: J T 2 F D e v ic e 6 Mbit/s JT2 Framer TXC-03702B DATA SHEET Product Preview 1 1 •■■!:.:= DESCRIPTION = The JT2 Framer JT2F is a CMOS VLSI device that provides the functions needed to frame a wideband payload to ITU G.704 and the NTT-specified 6312 kbit/s

TS12864

Contextual Info: L4M Device Level 4 Mapper TXC-03456 DATA SHEET Preliminary = • Maps an asynchronous 139.264 Mbit/s tributary into an AU-4/VC-4 STS-3c/SPE. • Nibble or byte 139.264 Mbit/s line interface - G.751 receive and transmit performance monitoring frame alignment, distant alarm

Contextual Info: E123MUX Device E1/E2/E3 MUX/DEMUX TXC-03361 DATA SHEET = • Multiplexer/demultiplexer for ITU-T Recommendations: G.742 E2 frame format G.751 (E3 frame format) DESCRIPTION = The E123MUX is a CMOS VLSI device that provides the E13 functions needed to multiplex and demultiplex

MP8791

Contextual Info: MP8791 C M O S , 2 M S P S , 12-Bit Analog-to-Digital Converter with Parallel Logic Interface Port C'EXAR FEATURES APPLICATIONS 12-Bit ADC with DNL = ±1 LSB, INL = ±2 LSB SNR > 60 dB Sampling Frequency < 2 MHz Internal Track and Hold: Input - 3 dB Frequency = 10 MHz

HC04

Contextual Info: % M i c r o July 1995 PRELIMINARY L in e a r ML6401 8-Bit 20 MSPS A/D Converter GENERAL DESCRIPTION FEATURES The ML6401 is a single-chip 8-bit 20 MSPS BiCMOS Video A/D Converter 1C, incorporating a differential input sample and hold, clock generation circuitry, and reference

Contextual Info: SIEMENS 2M X 32-Bit Dynamic RAM Module HYM 322030S/GS-50/-60/-70 Advanced Information • 2 097 152 words by 32-bit organization • 1 memory bank • Fast access and cycle time 50 ns access time 90 ns cycle time -50 version 60 ns access time 110 ns cycle time (-60 version)