FLIP-FLOP JT Search Results

ECL 10131

Abstract: signetics 10131 10131dc 10131N 10131F 25CC C30C62
Contextual Info: S ignetics 10131 Flip-Flop Dual D-Type Master-Slave Flip-Flop Product Specification ECL Products DESCRIPTION The 10131 is a Dual Master-Slave Flip­ Flop. Each flip-flop can be clocked sepa­ rately by holding the common Clock in the LOW state and using the Clock

ECL 100151

Abstract: 100151 PM710 100151F 100151Y
Contextual Info: Signetics 100151 Flip-Flop Hex D-Type Master-Slave Flip-Flop Product Specification ECL Products DESCRIPTION The 100151 contains six flip-flops with complement and data outputs, a master reset MR and a pair of common clock inputs. Data enter the flip-flop on the

TS 4142

Contextual Info: cn !33National Semiconductor 54F/74F175 Quad D Flip-Flop General Description Features The ’F175 is a high-speed quad D flip-flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D inputs is

Contextual Info: SCAN18374T SCAN18374T D Flip-Flop with TRI-STATE Outputs Literature Number: SNLS037 SCAN18374T D Flip-Flop with TRI-STATE Outputs General Description Features The SCAN18374T is a high speed, low-power D-type flip-flop featuring separate D-type inputs organized into dual

74107 pin diagram

Abstract: 74107 74LS107 74107 flip flop H/CI 74107 pin configuration 74LS107 1N3064 1N916 74LS LS107
Contextual Info: 74107, LS107 Signetics Flip-Flops Dual J-K Flip-Flop Product Specification Logic Products DESCRIPTION Th e '1 0 7 is a dual flip-flop with individual J, K, Clock and direct R eset inputs. The 7 4 1 0 7 Is a positive pulse-triggered flip­ flop. JK information is loaded into the

OBD II 2

Contextual Info: November 1994 Semiconductor & 54F/74F175 Quad D Flip-Flop General Description Features The ’F175 is a high-speed quad D flip-flop. The device is useful for general flip-flop requirements where do ck and clear inputs are common. The information on the p inputs is

74ACT374

Contextual Info: N ovem ber 1988 Revised January 1999 SEMICONDUCTOR TM 74AC374 • 74ACT374 Octal D-Type Flip-Flop with 3-STATE Outputs General Description Features The AC /AC T374 is a high-speed, low -pow er octal D-type flip-flop featuring separate D-type inputs for each flip-flop

LS534

Contextual Info: National Semiconductor DM74LS534 Octal D-Type Flip-Flop With TRI-STATE Outputs General Description The 'LS534 is a high speed, low power octal D-type flip-flop featuring separate D-type inputs for each flip-flop and TRI­ STATE outputs for bus oriented applications. A buffered

Contextual Info: MOTOROLA DUAL J-K FLIP-FLOP MC14027B The MC14Q27B dual J-K flip-flop has independent J, K, Clock {Q, Set S and Reset |R) inputs for each flip-flop. These devices may be used in control, register, or toggle functions. CMOS SSI • • Diode Protection on A ll Inputs

Contextual Info: 74LS377 Signetics Flip-Flop Octal D Flip-Flop With Clock Enable Product Specification Logic Products FEATURES • Ideal for addressable register applications • Clock Enable for address and data synchronization applications • Eight edge-triggered D flip-flops

Contextual Info: cn W e* National Semiconductor 54F/74F534 Octal D-Type Flip-Flop with TRI-STATE Outputs General Description Features The ’F534 is a high speed, low-power octal D-type flip-flop featuring separate D-type inputs for each flip-flop and TRI-STATE outputs for bus-oriented applications. A buff­

T374M

Contextual Info: 74AC374 • 74ACT374 Octal D-Type Flip-Flop with 3-STATE Outputs General Description Features The A C /AC T374 is a high-speed, low -pow er octal D-type flip-flop featuring separate D-type inputs fo r each flip-flop and 3-STATE outputs fo r bus-oriented applications. A buff­

Contextual Info: 3.3V CMOS 20-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS AND BUS-HOLD FEATURES: - CMOS technology. The ALVCH162821 device can be used as two 10-bit flip-flops or one 20-bit flip-flop. The 20-bit flipflops are edge-triggered D-type flip-flops. On the positive

Contextual Info: 3.3V CMOS 20-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS AND BUS-HOLD FEATURES: - CMOS technology. The ALVCH162821 device can be used as two 10-bit flip-flops or one 20-bit flip-flop. The 20-bit flipflops are edge-triggered D-type flip-flops. On the positive

74ls112 pin configuration

Abstract: 74ls112 function table 74LS112 74S112
Contextual Info: Signetics 74LS112, S112 Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION The '112 is a dual J-K negative edgetriggered flip-flop featuring individual J, K, Clock, Set and Reset inputs. The Set So and Reset (R q) inputs, when LOW,

PIN CONFIGURATION 7476

Abstract: pin diagram of 7476 7476 PIN DIAGRAM 7476 FUNCTION TABLE pin diagram of ttl 7476 7476 pin configuration LS 7476 7476 PIN DIAGRAM input and output 74LS76 J-K Flip-Flop 7476
Contextual Info: 7476, LS76 Sjgnetics Flip-Flops Dual J-K Flip-Flop Product Specification Logic Products DESCRIPTION The '76 is a dual J-K flip-flop with individual J, K, Clock, Set and Reset inputs. The 7476 is positive pulse-trig­ gered. JK information is loaded into the

Contextual Info: * SY10EL35 SY100EL35 JK FLIP-FLOP SYNERGY SEMICONDUCTOR DESCRIPTION FEATURES • 525ps propagation delay The SY10/100EL35 are high-speed JK Flip-Flops. The J/K data enters the m aster portion of the flip-flop when the clock is LOW and is transferred to the slave and,

Contextual Info: * SY10EL35 SY100EL35 JK FLIP-FLOP SYNERGY SEMICONDUCTOR DESCRIPTION FEATURES • 525ps propagation delay The SY10/100EL35 are high-speed JK Flip-Flops. The J/K data enters the m aster portion of the flip-flop when the clock is LOW and is transferred to the slave and,

HEF4013BP

Abstract: hEF4013 HEF4013BT HEF4013BPN HEF4013BTD HEF4013BP data
Contextual Info: HEF4013B \ , flip-flops V _ DUAL D-TYPE FLIP-FLOP The HEF4013B is a dual D-type flip-flop which features independent set direct Sq , clear direct (Cq ), clock inputs (CP) and outputs (0 ,0 ). Data is accepted when CP is LOW and transferred to the output on

Contextual Info: * SY10EL35 SY100EL35 JK FLIP-FLOP SYNERGY SEMICONDUCTOR DESCRIPTION FEATURES • 525ps propagation delay The SY10/100EL35 are high-speed JK Flip-Flops. The J/K data enters the m aster portion of the flip-flop when the clock is LOW and is transferred to the slave and,

Contextual Info: INTEGRATED CIRCUITS 74F273A Octal D flip-flop Product specification 1996 Mar 12 IC15 Data Handbook Philips Semiconductors PHILIPS Philips Semiconductors Product specification Octal D flip-flop 74F273A All outputs will be forced Low independently of Clock or Data inputs

JT40W

Abstract: CD4027B
Contextual Info: Z 537T CD4027B Types CMOS Dual J-K Master-Slave Flip-Flop High-Voltage Types {20-V o lt Rating The RCA-CD4027B is a single m onolithic chip integrated circuit containing tw o iden­ tical complementary-symmetry J-K masterslave flip-flops. Each flip-flop has provi­

3rw 44

Abstract: 74ALS109A 74ALS109AD 74ALS109AN SM15C
Contextual Info: 7 4 A L S 109 A . FLIP-FLOP 74ALS109A Dual J-K>osltive Edge-Triggered Flip-Flops With Set and Reset Product Specification DESCRIPTION The 'ALS109A is a dual positive edge-triggered JK-type flip-flop featuring individual J, R, Clock, Set and Reset inputs; also true and complemen­

Contextual Info: TOSHIBA T C74VH CT574AF/AFW/AFT TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC74VHCT574AF, TC74VHCT574AFW, TC74VHCT574AFT OCTAL D-TYPE FLIP-FLOP WITH 3 - STATE OUTPUT The TC74VHCT574A is an advanced high speed CMOS OCTAL FLIP-FLOP with 3 -STATE OUTPUT fabricated