FISU Search Results

H SC 945

Abstract: ELTH
Contextual Info: s tt-coupusm mp-aop \ MECL MC300 series MC308 A C -co u p led J -K flip-flop with d c S e t an d R e s e t in p u ts a n d b u ffe re d o u tp u ts fo r c o u n t e r an d sh ift re g iste r ap p licatio n s up to 15 M H z. FISURE 2 - INPUT WAVEFORM TO ESTABLISH MINIMUM T 06C LE FREQUENCY

Contextual Info: XRT86VX38A 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION JULY 2013 REV. 1.0.0 GENERAL DESCRIPTION The XRT86VX38A is an eight-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and Long-haul/Shorthual LIU integrated solution featuring R3 technology

IC HXJ 2038

Abstract: 1N52398 DB5T tfk 102 cny 70 hxj 2038 rca 40361 transistor rca 40362 TFK 680 CNY 70 Diode Equivalent 1N34A 2n5952 equivalent
Contextual Info: The Engineering Staff of TEXAS INSTRUMENTS INCORPORATED Components Group The T ransistor and Diode Data Book for Design Engineers T e x a s In s t r u m e n t s IN CO RPO RATED TYPE NUMBER INDEX GLOSSARY TRANSISTOR SELECTION GUIDES TRANSISTOR INTERCHANGEABILITY

CD 2399 GP

Abstract: 80387 DX Users Manual Programmers Reference
Contextual Info: PRByBJOODOÂIfflr in t e i Intel486 DX MICROPROCESSOR 168-Pin Grid Array Package High Performance Design — RISC Integer Core with Frequent Instructions Executing in One Clock — 25 MHz, 33 MHz, and 50 MHz Clock — 80, 106, 160 Mbyte/sec Burst Bus — CHMOS IV and CHMOS V Process

coprocessor

Contextual Info: in y Intel387 SX MATH COPROCESSOR N e w A u to m a tic P o w e r M a n a g e m e n t — L o w P o w e r C o n su m p tio n — T y p ic a lly 100 m A in D y n a m ic M o de, an d 4 m A in Id le M o d e S o c k e t C o m p a tib le w ith In te l3 8 7 Fam ily

Contextual Info: r a iO M O G O M V Military ì860tm 64-Bit M icro p ro cesso r • Compatible with Industry Standards — ANSI/IEEE Standard 754-1985 for Binary Floating-Point Arithmetic — 386 /j 486TM Microprocessor Data Formats and Page Table Entries ■ Parallel Architecture that Supports Up

hall marking code A04

Abstract: INTELDX4 write-through YSS 928
Contextual Info: INTEL486 PROCESSOR FAMILY • lntelDX4TM P ro c e s s o r — Up to 100-MHz Operation -Speed-M ultiplying Technology — 32-Bit Architecture — 16K-Byte On-Chip Cache — Integrated Floating-Point Unit — 3.3V Core Operation with 5V Tolerant I/O Buffers

Cyrix FasMath

Abstract: CX-83S87 cyrix 386SX fcom 7c DATA SHEET FOR OL 107 E SOLDER PEST FasMath 83D87 386SX CIRCUIT diagram 80386 83S87
Contextual Info: 83S87 User’s Manual High Performance CMOS Math Processor CYRIX CORP 3bE » H SSñ^ñn □ GQDlB'ì fi • T—49—1 2-05 FasMath CX-83S87 User's Manual January, 1990 o * P.O. Box 850118 Richardson, TX 76085-0118 CYR CYRIX CORP 3bE D ■ 2 5 ö t filici □ □ D D I M Q

DS33R41

Abstract: DS21455 DS21458 DS2155 DS33Z41
Contextual Info: DS33R41 Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 Transceivers www.maxim-ic.com GENERAL DESCRIPTION FEATURES 10/100 IEEE 802.3 Ethernet MAC MII and RMII Half/Full Duplex with Automatic Flow Control The DS33R41 extends a 10/100 Ethernet LAN

apm 7120 ic

Abstract: FALC56 apm 7120 circuit diagram of moving LED message display maxim rs232 protection overvoltage QuadFALC RJ45 to DB9F cable adapter PEB22554 v1.3 LSSU message display on LED
Contextual Info: ICs for Communications Evaluation System for QuadFALC EASY22554 Tool Description 12.99 DS 2 • EASY22554 Tool Description Revision History: Current Version: 12.99 Previous Version: Tool Description EASY22554 03.99 DS1 Page Page in previous (in current Version

mm-100-xxx

Abstract: microprocessor 80286 internal architecture mm-100-xx AMD "model 8" AMD Family 10h Processor Electrical Data Sheet mmx 166 id-20 innovation 80286 address decoder Ac-37-k amd 15h power
Contextual Info: Preliminary Information AMD-K6 -IIIE+ Embedded Processor Data Sheet Publication # 23543 Rev: A Amendment/0 Issue Date: September 2000 2000 Advanced Micro Devices, Inc. All rights reserved. The contents of this document are provided in connection with Advanced Micro

Developer

Abstract: 243007 weighing scale code example 242690 intel 8086 241429 241429 intel intel 243007 CL1101 ptz decoder
Contextual Info: Intel Architecture Optimization Manual Order Number 242816-003 1997 5/5/97 11:38 AM FRONT.DOC Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions

8088 assembly language manual

Abstract: 8086 assembly language reference manual ptz decoder architecture of pentium microprocessor intel Programmers Reference Manual 243007 intel 8086 newton raphson power flow model isa bus interfacing with microprocessor 8088 IA-32 Intel Architecture Software Developers Manual
Contextual Info: Intel Architecture Optimization Reference Manual Copyright 1998, 1999 Intel Corporation All Rights Reserved Issued in U.S.A. Order Number: 245127-001 Intel® Architecture Optimization Reference Manual Order Number: 730795-001 Revision Revision History

Contextual Info: 1.8A Switching Regulator w ith 5V, 100mA Linear Regulator w ith Watchdog, RESET and ENABLE D escrip tion The CS-5111 is a dual output power sup­ ply integrated circuit. It contains a 5V ±2%, 100mA linear regulator, a watchdog timer, a linear output voltage monitor to

XD 5252 F

Abstract: intel 8295 microprocessor STi 5197 register configuration Mistral oscillator 20532 20542 marking S4 53A CRC-16 CRC-32 RFC1662
Contextual Info: ICs for Communications DMA Integrated Serial Communication Controller MISTRAL PEB 20542 Version 1.1 PEF 20542 Version 1.1 Preliminary Data Sheet 08.99 DS 1 • PEB 20542, PEF 20542 Revision History: Current Version: 08.99 Previous Version: 07.99 Page in previous

DS26521

Abstract: BTS 308 EC17 pinout of bel 187 transistor rspc 193 ec5 BBC FTL 3-2 G.SHDSL Industry Single-Chip DS2155 DS2156
Contextual Info: DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS33R11 extends a 10/100 Ethernet LAN segment by encapsulating MAC frames in HDLC or X.86 LAPS for transmission over a T1/E1/J1 data stream. §

PROCESSOR

Abstract: mp 9141 es dc-dc mp 9141 es CX5520 GXm-180B 2.9V 70C power module si 3101 schematic diagram Geode GXm Processor tag 8514 30054 gxm-266b
Contextual Info: Geode GXm Processor Integrated x86 Solution with MMX Support General Description The National Semiconductor Geode™ GXm processor is an advanced 32-bit x86 compatible processor offering high performance, fully accelerated 2D graphics, a 64-bit synchronous DRAM controller and a PCI bus controller,

CM603

Contextual Info: 6DI3OA-O5O 30a Ä ± / < 7 — Ì V ; Outline Drawings , < n - \ = 7 > V 'T s ^ i> z l - ; u POWER TRANSISTOR MODULE (10), H.& j I9.5~ . H .5 . 1|,& . (1p}| F e a tu re s • 7 '} — X ' f <J ' s '? $ 4 + — K r t/K • liF E ^ 'iS i.' • S6i&Jfi In c lu d in g 'F re e W h e e lin g D iode

FDS 4468

Abstract: HBT 01 - 04G INTEL 486 sx sl pinout 240950 JVC 4580 fds 4418 TOT - 4301 INTEL DX4 241199 Intel DX4TM
Contextual Info: intj, INTEL486 PROCESSOR FAMILY • Write-Back Enhanced lntelDX4™ Processor — Up to 100-MHz Operation — Speed-Multiplying Technology — 32-Bit Architecture — 16K-Byte On-Chip Write-Back Cache — Integrated Floating-Point Unit — 3.3V Core Operation with 5V Tolerant

manual for Misa

Abstract: ruy 1015
Contextual Info: AMD£I Am486 DX/DX2 Microprocessor Hardware Reference Manual AMD's Marketing Communications Department specifies environmentally sound agricultural irks and recycled papers, making this book highly recyclable. Am486™DX/DX2 Microprocessor Hardware Reference

10KHZ

Abstract: 20L10 20RA10 74ALS 74HC 74HCT EP512
Contextual Info: F & I— J ^V J a \ 12 MACROCELL EPLD FEATURES GENERAL DESCRIPTION H igh Perform ance lo g ic replacem ent for T T L and 74HC or 74HCT SSI and M SI logic. High Speed, tpd = 25ns, and 40M H z operating frequency. "Zero Pow er” 150 f/A Standby Current . Twelve M acrocells with configurable I/O archi­

00A75

Abstract: INTEL Core i7 860 J 80222 lm 6358 J1 3009-2 271121 Texture mapping CC1105 Intel i860
Contextual Info: P K H IL D fiflD M M V MILITARY i860 XR 32/64-BIT MICROPROCESSOR • Parallel Architecture that Supports Up to Three Operations per Clock — One Integer or Control Instruction per Clock — Up to Two Floating-Point Results per Clock ■ High Performance Design

G6003

Contextual Info: DS33R41 Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 Transceivers www.maxim-ic.com GENERAL DESCRIPTION FEATURES 10/100 IEEE 802.3 Ethernet MAC MII and RMII Half/Full Duplex with Automatic Flow Control The DS33R41 extends a 10/100 Ethernet LAN

str w 6556 a

Abstract: Lg tv str 6554 siemens b 58 468 la intel 80 LG tv str 6554 circuit diagram str x 6556 tv power supply str 6556 SIS 968 str w 6556 equivalent A5GND str 6556
Contextual Info: Freescale Semiconductor, Inc. Freescale Semiconductor, Inc. MC68360 QUad Integrated Communications Controller User’s Manual For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc. ii