860TM Search Results

Contextual Info: r a iO M O G O M V Military ì860tm 64-Bit M icro p ro cesso r • Compatible with Industry Standards — ANSI/IEEE Standard 754-1985 for Binary Floating-Point Arithmetic — 386 /j 486TM Microprocessor Data Formats and Page Table Entries ■ Parallel Architecture that Supports Up

Contextual Info: in tj. 28F400BX-T/B, 28F004BX-T/B 4 MBIT 256K x16, 512K x8 BOOT BLOCK FLASH MEMORY FAMILY • x8/x16 Input/Output Architecture — 28F400BX-T, 28F400BX-B — For High Performance and High Integration 16-bit and 32-bit CPUs ■ Very High-Performance Read

00A75

Abstract: INTEL Core i7 860 J 80222 lm 6358 J1 3009-2 271121 Texture mapping CC1105 Intel i860
Contextual Info: P K H IL D fiflD M M V MILITARY i860 XR 32/64-BIT MICROPROCESSOR • Parallel Architecture that Supports Up to Three Operations per Clock — One Integer or Control Instruction per Clock — Up to Two Floating-Point Results per Clock ■ High Performance Design

k 4431

Contextual Info: in te i 28F200BX-T/B, 28F002BX-T/B 2 MBIT 128K x 16,256K x 8 BOOT BLOCK FLASH MEMORY FAMILY x6/x16 Input/Output Architecture — 28F200BX-T, 28F200BX-B — For High Performance and High Integration 16-bit and 32-bit CPUs Very High-Performance Read — 60/80 ns Maximum Access Time

PAL16L8 programming algorithm

Abstract: N85C220 85C220 pal16r8 programming algorithm 85C224-66 D85C220-66 intel PLD d85c220 gal 16v8 programming algorithm
Contextual Info: in te i 85C220/85C224-100, -80 AND -66 FAST REGISTERED SPEED TSU, TS0 8-MACROCELL PLDs These register optimized timing PLDs offer superior design features: • Low-Power, High-Performance Upgrade for SSI/MSI Logic and Bipolar PALs* High-Performance Systems

Contextual Info: M85C220 FAST 1-MICRON CHMOS 8-MACROCELL jmPLD Military m High-Performance, Low-Power Upgrade • ■ ■ ■ ■ See Packaging Spec., Order #231368 ■ Military Temperature Range: —55°C to +125°C(Tc) O Csi cs o in 00 2 IN P 1 /C L K C 1 IN P 2 C 2 IN P 3 C

28F400BC

Abstract: AB28F200BX-B90 29050 AB28F
Contextual Info: M M /M'Vam OKllF ISIMiaTO Kl A28F200BX-T/B 2-MBIT 128K x 16, 256K x 8 BOOT BLOCK FLASH MEMORY FAMILY A utom otive • Very High-Performance Read — 90 ns Maximum Access Time — 45 ns Maximum Output Enable Time ■ x8/x16 Input/Output Architecture — A28F200BX-T, A28F200BX-B

MTA02

Abstract: i860Xp MT 8222 Intel 82495 Cache Controller 3ce-14 LR1 D09 ahy 103 i860 64-Bit Microprocessor Performance Brief MCache Second Level Cache-Controller
Contextual Info: in t e ! 82495XP CACHE CONTROLLER/ 82490XP CACHE RAM Two-Way, Set Associative, Secondary Cache for i860 XP Microprocessor 50 MHz “No Glue” Interface with CPU Configurable — Cache Size 256 or 512 Kbytes — Line Width 32, 64 or 128 Bytes — Memory Bus Width 64 or 128 Bits

ccd bm

Contextual Info: Ä i f Ä i OMIFOKöMTTIM irrte* 28F400BX-T/B, 28F004BX-T/B 4 MBIT 256K x16, 512K x8 BOOT BLOCK FLASH MEMORY FAMILY x8/x16 Input/Output Architecture — 28F400BX-T, 28F400BX-B — For High Performance and High Integration 16-bit and 32-bit CPUs x8-only Input/Output Architecture

Contextual Info: i860 64-BIT MICROPROCESSOR • Compatible with Industry Standards — ANSI/IEEE Standard 754-1985 for Binary Floating-Point Arithmetic — 386™ /i486TM Microprocessor Data Formats and Page Table Entries — JEDEC 168-pin Ceramic Pin Grid Array Package see Packaging

Contextual Info: inU 28F200BX-T/B, 28F002BX-T/B 2-MBIT 128K x 16, 256K x 8 BOOT BLOCK FLASH MEMORY FAMILY • x8/x16 Input/Output Architecture — 28F200BX-T, 28F200BX-B — For High Performance and High Integration 16-bit and 32-bit CPUs ■ x8-only Input/Output Architecture

Contextual Info: Ä ID W A M < & g DKlF [^ôiÆ ÂTB©M in te i M85C224 FAST 1-MICRON CHMOS 8-MACROCELL jaPLD Up to 22 Inputs 14 Dedicated & 8 I/O and 8 Outputs High-Performance, Low-Power Upgrade for SSI/MSI Logic and Bipolar PALs* in Intel386 , i486™, i860™, 80960 Series,

GAL16Y8A

Abstract: PAL16L8 programming algorithm gal 16v8 programming algorithm 85C224 PAL12L10N ep330 intel 2107 GAL-2 85c224-66 85C220
Contextual Info: INTEL CORP MEMORY/PL] / 5bE D • M Ö E b l 7 b D 0 7 7 S b D 7^5 « I T L S in y -0 °\ 85C220/85C224-100, -80 AND -66 REGISTER OPTIMIZED TIMING FAST 1-MICRON CHMOS 8-MACROCELL juPLDs T hese register optimized timing /xPLDs of­ fer superior design features:

TC8601

Contextual Info: O K I Semiconductor MTC8601M16-280x2 fla sh M emory ca rd DESCRIPTION The MTC8601M16-250A2, MTC8601M16-250B2 and M TC8601M16-250C2 are IMbytes flash memory cards in conform ity with the IC mem ory card guideline Ver. 4 of the Japan Electronic Industry Development Association, Inc.

Intel i860

Contextual Info: INTEL CORP UP/PRPHLS bflE » • 4ñ2bl7S Dia^flSb in te i i860 XR 64-BIT MICROPROCESSOR ■ Parallel Architecture that Supports Up to Three Operations per Clock — One Integer or Control Instruction per Clock — Up to Two Floating-Point Results per

INTEL ES

Abstract: p28f001 BXT150 28F001BX-B 28F001BX-T
Contextual Info: in te i 1-MBIT 128Kx 8 BOOT BLOCK FLASH MEMORY 2 8 F 0 0 1 B X - T /2 8 F 0 0 1 B X -B /2 8 F 0 0 1 B N - T /2 8 F 0 0 1 B N -B m High-lntegration Blocked Architecture — One 8 KB Boot Block w /Lock Out — Two 4 KB Parameter Blocks — One 112 KB Main Block

XT150

Abstract: xt90
Contextual Info: in tj 28F001BX-T/28F001BX-B 1M 128K X 8 CMOS FLASH MEMORY High Integration Blocked Architecture — One 8 KB Boot Block w/Lock Out — Two 4 KB Parameter Blocks — One 112 KB Main Block High-Performance Read — 70/75 ns, 90 ns, 120 ns, 150 ns Maximum Access Time

FGT 313

Contextual Info: in te i ¡860 XR 64-BIT MICROPROCESSOR • Parallel Architecture that Supports Up to Three Operations per Clock — One Integer or Control Instruction per Clock — Up to Two Floating-Point Results per Clock Compatible with Industry Standards — ANSI/IEEE Standard 754-1985 for

Contextual Info: in te * MILITARY i860 64-BIT MICROPROCESSOR Parallel Architecture that Supports Up to Three Operations per Clock — One Integer or Control Instruction per Clock — Up to Two Floating-Point Results per Clock • Compatible with Industry Standards — ANSI/IEEE Standard 754-1985 for

FGT 313

Abstract: N06010 a3058c 271121 intel i860
Contextual Info: [ p fô iy iiM A O W in te L MILITARY i860 XR 32/64-BIT MICROPROCESSOR Parallel Architecture that Supports Up to Three Operations per Clock — One Integer or Control Instruction per Clock — Up to Tw o Floating-Point Results per Clock High Perform ance Design

ba 6414 fs

Abstract: RTL 2832 A80860XP i860Xp 80860XR 80860XP equivalent of transistor tt 2148 transistor x 313 ca 361 e ic 82490XP
Contextual Info: intei I860 XP MICROPROCESSOR • Parallel Architecture that Supports Up to Three Operations per Clock — One Integer or Control Instruction — Up to Two Floating-Point Results ■ High Performance Design — 40/50 MHz Clock Rate — 100 Peak Single Precision MFLOPS

85C508

Abstract: Intel 85C508 290175 incir
Contextual Info: i n t o l. 85C508 FAST 1-MICRON CHMOS DECODER/LATCH juPLD • High-Performance Programmable Logic Device for High-Speed Microprocessorto-Memory Decode ■ 16 Dedicated Inputs for Address/Data Bus Decoding; 8 Latched Outputs; 1 Global Latch Enable ■ Supports Intel386 , i468TM, ¡860tm,

486TM

Contextual Info: I N T E L CORP PIEPIOR Y / P L D / SbE D • 4fl5bl7L> OD7ti44D 0 2 e! ■ ITL2 in te l 28F400BX-T/B, 28F004BX-T/B 4 MBIT (256K x16, 512K x8 BOOT BLOCK FLASH MEMORY FAMILY x8/x16 Input/Output Architecture — 28F400BX-T, 28F400BX-B — For High Performance and High

AB28F

Contextual Info: A E W Ä N K S H OKllF ISIMlÄflrö Kl i n y A28F400BX-T/B 4-MBIT 256K x16, 512K x8 BOOT BLOCK FLASH MEMORY FAMILY A u to m o tiv e Very High-Performance Read — 90 ns Maximum Access Time — 45 ns Maximum Output Enable Time x8/x16 Input/Output Architecture