ECL NOT Search Results

Contextual Info: bel ACTIVE DELAY LINES cont. Style ECL ECt ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL 10KH 5 Tap 10KH 5 Tap 10KH 5 Tap 10KH 5 Tap 10KH 5 Tap 10KH 5 Tap 10K H 5 Tap 10KH 5 Tap 10KH 5 Tap 10KH 5 Tap 10KH 5 Tap 10KH 5 Tap 10KH 5 Tap ECL ECL ECL ECL ECL ECL

Contextual Info: TNETA1545 DUAL DIFFERENTIAL PSEUDO-ECL TO ECL TRANSLATORS AND DUAL DIFFERENTIAL ECL TO PSEUDO-ECL TRANSLATORS SDNS005B - SEPTEMBER 1993 - REVISED OCTOBER 1995 • Dual ECL to Pseudo-ECL and Pseudo-ECL to ECL Translators • Single 5-V Power Supply • Advanced BiCMOS Technology

TNETA1545

Contextual Info: TNETA1545 DUAL DIFFERENTIAL PSEUDO-ECL TO ECL TRANSLATORS AND DUAL DIFFERENTIAL ECL TO PSEUDO-ECL TRANSLATORS SDNS005B – SEPTEMBER 1993 – REVISED OCTOBER 1995 D D D D D DW PACKAGE TOP VIEW Dual ECL to Pseudo-ECL and Pseudo-ECL to ECL Translators Single 5-V Power Supply

9434

Abstract: CY101E383 EME-6300H
Contextual Info: Reliability Report QTP# 94346/95255, Version 1.0 June, 1996 BiCMOS ECL-TTL/TTL-ECL TRANSLATOR MARKETING PART NUMBERS DESCRIPTION CY101E383 ECL/TTL/ECL Translator and High Speed Bus Driver CY10E383 ECL/TTL/ECL Translator and High Speed Bus Driver CYPRESS SEMICONDUCTOR

SG86A

Abstract: SG53A sg72a LVEP17 MC100ELxxx EP809 LVEL40 SLVS TR30 AND8020
Contextual Info: AN1568/D Interfacing Between LVDS and ECL Prepared by: Paul Lee Logic Applications Engineer ON Semiconductor http://onsemi.com APPLICATION NOTE ECL levels Today’s applications typically use ECL devices in the PECL mode. PECL Positive ECL is nothing more than

CAN split termination

Abstract: SG86A SG53A AN1568
Contextual Info: AN1568/D Interfacing Between LVDS and ECL Prepared by: Paul Lee Logic Applications Engineer ON Semiconductor http://onsemi.com APPLICATION NOTE ECL levels Today’s applications typically use ECL devices in the PECL mode. PECL Positive ECL is nothing more than

Contextual Info: MC10H604 MC100H604 MOTOROLA Product Preview REGISTERED HEX TTL TO ECL TRANSLATOR Registered Hex TTL/ECL Translator The MC1 OH/100H604 is a 6-bit, registered, dual supply TTL to ECL translator. The de­ vice features differential ECL outputs as well as a choice between either a differential ECL

10H645

Abstract: E211 MC10E111 MPC973 AN1405
Contextual Info: AN1405/D ECL Clock Distribution Techniques Prepared by Todd Pearson ECL Applications Engineering http://onsemi.com APPLICATION NOTE This application note provides information on system design using ECL logic technologies for reducing system clock skew over

Contextual Info: AN1405 Application Note ECL Clock Distribution Techniques Prepared by Todd Pearson ECL Applications Engineering This application note provides information on system design using ECL logic technologies for reducing system clock skew over the alternative CMOS and TTL

CY101E383

Abstract: E383 R2170 ecl 84
Contextual Info: E383 CY101E383 ECL/TTL/ECL Translator and High-Speed Bus Driver Features • BiCMOS for optimum speed/power • High speed max. — 3.0 ns tPD TTL-to-ECL Functional Description The CY101E383 is a new-generation TTL-to-ECL and ECL-to-TTL logic level translator designed for high-perfor-

ZO 103

Abstract: bourns capacitor network 4610H-805-151 4610H803201104 ECL 802 SIP10K
Contextual Info: Features • ■ ■ For information on ECL Terminators, download Bourns' ECL Terminator Application Note. Optimize data transmission in ECL systems through proper termination between drivers and receivers Minimize overshoot, undershoot, and ringing while increasing noise immunity

10H645

Abstract: AN1405 E211 MC10E111 MPC973
Contextual Info: AN1405 Application Note ECL Clock Distribution Techniques Prepared by Todd Pearson ECL Applications Engineering This application note provides information on system design using ECL logic technologies for reducing system clock skew over the alternative CMOS and TTL

AN-1405

Contextual Info: A N 1405 Application Note ECL Clock Distribution Techniques Prepared by Todd Pearson ECL Applications Engineering This application note provides information on system design using ECL logic technologies for reducing system clock skew over the alternative CMOS and TTL

10H645

Abstract: AN1405 DL140 E211 MC10E111 MPC973
Contextual Info: AN1405 Application Note ECL Clock Distribution Techniques Prepared by Todd Pearson ECL Applications Engineering This application note provides information on system design using ECL logic technologies for reducing system clock skew over the alternative CMOS and TTL

mb 3712

Contextual Info: SK10/100EL91W Triple PECL to ECL/LVECL and LVPECL to ECL/LVECL Translator HIGH-PERFORMANCE PRODUCTS Description Features The SK10/100EL91W is a triple PECL to ECL/LVECL and LVPECL to ECL/LVECL translator. It is fully compatible with MC100EL91 and MC100LVEL91. The

Contextual Info: Freescale Semiconductor, Inc. Order number: AN1405 Rev 1, 09/2001 APPLICATION NOTE AN1405 ECL Clock Distribution Techniques By: Todd Pearson ECL Applications Engineering ABSTRACT This application note provides information on system design using ECL logic technologies for reducing system clock skew

ecl 10K

Abstract: RCD Components E1001 E1004 E1008 E103 E105 SCHEMAT
Contextual Info: PRELIMINARY ECL DIGITAL DELAY LINES -5-41-5 - ECL 10K INTERFACED -5-41-5 - ECL 100K INTERFACED FEATURES TYPE E105 - ECL 10K 5 TAP Tap Delay nS 3 20 4 25 5 30 6 2X Total Delay Pulse Spacing 5X Total Delay -1.0V provided by open emitter ECL 10K gate

XEP56V

Abstract: SY100EP56VK4GTR MC100EP56DT MC100EP56DTR2 SY100EP56V SY100EP56VK4G SY100EP56VK4I SY100EP56VK4ITR
Contextual Info: ECL Pro 3.3V/5V PECL/ECL 3GHz DUAL DIFFERENTIAL 2:1 MULTIPLEXER Micrel, Inc. SY100EP56V ECL Pro™ SY100EP56V FEATURES • Dual, fully differential 2:1 PECL/ECL multiplexer ■ Guaranteed AC parameters over temperature/ voltage: • > 3GHz fMAX toggle

XEP56V

Contextual Info: ECL Pro 3.3V/5V PECL/ECL 3GHz DUAL DIFFERENTIAL 2:1 MULTIPLEXER Micrel, Inc. SY100EP56V ECL Pro™ SY100EP56V FEATURES • Dual, fully differential 2:1 PECL/ECL multiplexer ■ Guaranteed AC parameters over temperature/ voltage: • > 3GHz fMAX toggle

Contextual Info: MOTOROLA Order Number: AN1405/D SEMICONDUCTOR TECHNICAL DATA Rev 1, 09/2001 AN1405 ECL Clock Distribution Techniques Prepared by: Todd Pearson ECL Applications Engineering Abstract This application note provides information on system design using ECL logic technologies for reducing system clock skew

Contextual Info: MOTOROLA Order Number: AN1405/D SEMICONDUCTOR TECHNICAL DATA Rev 1, 09/2001 AN1405 ECL Clock Distribution Techniques Prepared by: Todd Pearson ECL Applications Engineering Abstract This application note provides information on system design using ECL logic technologies for reducing system clock skew

H604

Abstract: MC100H604 MC100H604FN MC10H604 MC10H604FN
Contextual Info: MC10H604, MC100H604 Registered Hex TTL to ECL Translator The MC10H/100H604 is a 6–bit, registered, dual supply TTL to ECL translator. The device features differential ECL outputs as well as a choice between either a differential ECL clock input or a TTL

marking Ed11

Contextual Info: PECL, ECL, LVDS Page 1 - 6 Pl tronics,. Inc. 19013 36th Ave. W, Suite H Lynnwood, WA 98036 USA Manufacturer of High Quality Frequency Control Products ED1145M ECL Series Full Size Metal Thru-Hole ECL Oscillator Differential or NonDifferential ECL Output without Enable/Disable

PLCC-28

Abstract: H604 MC100H604 MC10H604 MC10H604FN
Contextual Info: MC10H604, MC100H604 Registered Hex TTL to ECL Translator Description The MC10H/100H604 is a 6−bit, registered, dual supply TTL to ECL translator. The device features differential ECL outputs as well as a choice between either a differential ECL clock input or a TTL clock