signal path designer
Contextual Info: PRELIMINARY DEVICE SPECIFICATION Q20000 SERIES ECL/TTL TURBO" LOGIC ARRAYS 020000 FEATURES • Up to 24000 gates, channelless architecture • 100ps equivalent gate delays • Ultra low power ,5-1.0mW/gate • 10K, 10KH, 100K ECL and mixed ECL/TTL capability
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q20000100pssa/d1203-1089signal path designer |
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CTR34
Abstract: FGE2000 BL33B DFI01 Fairchild ZN 1010 L1332 JKI02 ctr-34 SHR04 OAI43
Contextual Info: NATL SEMICOND -CMEnORY> □2E D | ts D iia b □□bi3n ? I FGE Series ECL Gate Arrays FAIRCHILD A Schlumberger Company Description FGE Series Features The FGE Series of ECL gate arrays are the fastest silicon gate arrays commercially available. These advanced ECL gate ar
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f100k225-picosecondandrs003ttrs103+11controller/16-outctr34fge2000bl33bdfi01fairchild zn 1010l1332jki02ctr-34shr04oai43
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L100k
Contextual Info: Single PRELIMINARY , , Copy v “ 1 3 l l Q 1 0 DEVICE SPECIFICATION \ QM1600S ECL/TTL LOGIC ARRAY WITH RAM FEATURES ECL LOGIC AND RAM COMBINED 002335 The QM1600S is configured to provide up to 1600 equi valent gates of high speed ECL logic coupled with 1280
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qm1600sqm1600l100k |
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am2022
Abstract: am22 full adder circuit using xor and nand gates AM2031 AM2024 AM2051 t950 half adder circuit using nor and nand gates ax253 AM290
Contextual Info: Am 3525 Mask-Programmable Gate Array With ECL RAM PRELIMINARY > 3 DISTINCTIVE CHARACTERISTICS Up to 3718 equivalent gates - 416 internal cells - Up to 135 l/O s 1152 bits of ECL RAM 1K with byte-wide parity - Worst case T a a (access time) = 5.5 ns High-performance, low-power ECL gates
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am3525tc002800wf0109807321a+11d7322aam2022am22full adder circuit using xor and nand gatesam2031am2024am2051t950half adder circuit using nor and nand gatesax253am290
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Fairchild ZN 1010
Abstract: GENERAL INSTRUMENT west 2500 ic ZN 415 FGE2000
Contextual Info: FGE Series ECL Gate Arrays PAIRCHIL.D A Schlum berc T'HO Qr>y 005596 January 1986 Description U/v\A m b The FGE Series of ECL gate arrays are the fastest silicon gate arrays com m ercially available. These advanced ECL gate arrays, ranging from 100 to 2840 equivalent gates, offer
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f100kfge250028ngtonfairchild zn 1010+3general instrument west 2500ic zn 415fge2000
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TR20X3
Abstract: DFI01 OR02D
Contextual Info: December 1989 FGA S eries A S PE C T- ECL G ate A rrays General Description The FGA Series is a new generation of ECL gate arrays based on National’s ASPECT process. These advanced ECL gate arrays, ranging from 200 to over 30,000 equiva lent gates, offer typical internal propagation delays of
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tr20x3dfi01or02d |
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FGE0500
Abstract: FGE2000 FGE2500 F100K ECL 300 series and design guide Fairchild 100K series ECL Fairchild ZN 1010 1240 picosecond la 4440 LA 4440 circuit diagram PS-1050
Contextual Info: FGE Series ECL Gate Arrays F A IR C H IL D A Schlumberc J/n A 005596 January 1986 n Description 0r>y ^ Gate Array Division FiC The FGE Series of ECL gate arrays are the fastest silicon gate arrays commercially available. These advanced ECL gate arrays, ranging from 100 to 2840 equivalent gates, offer
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f100k225j3fge0500fge2000+8fge2500f100k ecl 300 series and design guidefairchild 100k series eclfairchild zn 10101240 picosecondla 4440la 4440 circuit diagramps-1050
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Q20P010
Abstract: Q20M100 carry look ahead adder Q20080 Q20P025 Q20025 vernier Q20000 Q20004 Q20010
Contextual Info: D EV IC E SP EC IFIC A TIO N LOGIC ARRAYS Q20000 “TURBO” ECL/TTL Q20000 FEATURES Figure 6. Q20080 Die • • • • • • • • • • Up to 18,777 gates, channelless architecture 100 ps equivalent gate delays Low power 0.5-1.0 mW/gate 10K, 10KH, 10OK ECL and mixed ECL/TTL capability
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q200000q03rlq20p010q20m100+7carry look ahead adderq20080q20p025q20025vernierq20004q20010
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signal path designer
Contextual Info: PRELIMINARY D E V IC E S P E C IF IC A T IO N 320000 SERIES ECL/TTL "TURBO" LOGIC ARRAYS 020000 FEATURES PERFORMANCE SUMMARY PARAMETER Typical gate delay* Maximum toggle frequency Maximum TTL input frequency Maximum TTL output frequency Maximum ECL input frequency
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/d1203-0589signal path designer |
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Q3500
Abstract: 300MHZ ECL100K ECL10K QM1600 QM1600S bcd counter using t flip flop diagram Vcc-1105
Contextual Info: Single PRELIMINARY ^ Copy .\ / •— “ * r 1 vi j I \ i U * * 1 11 ■ Z Z H / v Z Z Z z DEVICE SPECIFICATION QM1600S ECL/TTL LOGIC ARRAY WITH RAM FEATURES ECL LOGIC AND RAM COMBINED The Q M 1600S is con figu red to pro vid e up to 1600 e q u i valent ga tes of high spe ed ECL logic c o u p le d with 1280
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qm1600sqm1600b96tihfibq3500+5300mhzecl100kecl10kbcd counter using t flip flop diagramvcc-1105
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HA 1370 schematics
Abstract: CMOS XNOR XOR NAND2 NAND3 ic ttl and not xor nor xnor or MICRON POWER RESISTOR 2W ECL IC NAND
Contextual Info: PRELIMINARY Semiconductor December 1990 NGM Series ABiC BiCMOS/ECL Gate Arrays General Description Features The NGM Series is a new family of mixed ECL and BiCMOS gale arrays based on National’s revolutionary 0.8 micron drawn ABiC BiCMOS process. The NGM Series is the first
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tl/u/10861-4ha 1370 schematicscmos xnor xor nand2 nand3ic ttl and not xor nor xnor or+2micron power resistor 2wecl ic nand
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ECL2515
Abstract: ECL2516 ECL2500
Contextual Info: TYPES ECL2515, ECL2516 EMITTER-COUPLED-LOGIC ARITHMETIC MODULES ECL INTEGRATED CIRCUITS ra -h ECL2500 SERIES EMITTER-COUPLED-LOGIC ECL ARITHM ETIC MODULES FOR APPLICATION IN ULTRA-HIGH-SPEED D IG ITAL SYSTEMS c< r "0 i-m mw Hm i? 02 o-01 f- m description
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ecl2515ecl2516ecl2500 |
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AM2019
Abstract: 2-bit half adder layout AX253 AX201 AM2001 AX261
Contextual Info: * Am3525 Mask-Programmable Gate Array With ECL RAM PRELIMINARY > 3 DISTINCTIVE CHARACTERISTICS • • • Up to 3718 equivalent gates - 416 internal cells - Up to 135 l/O s 1152 bits of ECL RAM 1K with byte-wide parity - Worst case T a a (access time) = 5.5 ns
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am3525tc0028007321a7322a+6am20192-bit half adder layoutax253ax201am2001ax261
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Silicon npn TRANSISTOR TCNL 100
Abstract: tcnl 100 TRANSISTOR TCNL 100 ECL IC NAND MUX4E schematic of TTL XOR Gates TSN2 tcnl transistor ic xnor XOR23
Contextual Info: T & T MELEC I C b4E D • DOSGQEb OOlGSlfc, Preliminary Data Sheet May 1992 a TG2 ■ ATT? &t M icroelectronics a t BEST-1 Series High-Performance ECL Gate Arrays Features Description ■ 1,000 and 4,000 equivalent logic gates The BEST-1 Series High-Performance ECL Gate
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005002b001021bsilicon npn transistor tcnl 100tcnl 100+8transistor tcnl 100ecl ic nandmux4eschematic of ttl xor gatestsn2tcnl transistoric xnorxor23
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LT016
Abstract: LT08 YD-350 ecu schematics AIX200 LT08C LBd8 AIX2024 COF2001
Contextual Info: ADV faCRO PLA/PLE/ARRAYS 13E D Am353 b oas?sat, aoaasib 1 1 Mixed ECL/TTL I/O Mask-Programmable Gate Array > 3 DISTINCTIVE CHARACTERISTICS Integrated up to 410 ECL-equivalent gates in a 24-pin slim DIP , to eliminate "g lu e " logic, resulting in reduced
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atn35324-pinais-wcp-15m-9/88-0lt016+8lt08yd-350ecu schematicsaix200lt08clbd8aix2024cof2001
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AM2001
Abstract: AM223 full adder circuit using nor gates AM2005 AX202 AM2031 AM319 abx2002 full adder circuit using xor and nand gates ax253
Contextual Info: Am 3500 Mask-Programmable ECL G ate Array PRELIM IN ARY > 3 DISTINCTIVE CHARACTERISTICS • • Up to 4988 equivalent gates - 576 internal cells - Up to 134 l/O s H igh-perform ance, low -pow er ECL gates - W orst case Tpcj = 0.6 ns Hi-Speed = 0.7 ns (Medium)
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am3500tc002800wf0109807321a+117322aam2001am223full adder circuit using nor gatesam2005ax202am2031am319abx2002full adder circuit using xor and nand gatesax253
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SH100E
Abstract: siemens SH100E elxr siemens Nand gate SH100E5 TRANSISTOR K 2191
Contextual Info: 7 1991 SIEMENS ASIC Product Description SH100E ECL/CML Gale Amy Family FEATURES • Gate complexities from 1,500 to 16,000 gates ■ 120 ps gate delay, 90 ps differential • 1.5 GHz D flip-flop, 1.7 GHz differential ■ Both ECL and CML macro families ■ TTL I/O available
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sh100e10kh/100km33s001siemens sh100e+4elxrsiemens nand gatesh100e5transistor k 2191
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ET3004M
Abstract: CS31E 4input nor gate ET-3004M
Contextual Info: FUJITSU MICROELECTRONICS 31E D • 374^7^2 D014b2b 7 ■ F M I cP February 1990 Edition 1.1 - FUJITSU D A TA S H EE T ET2004M, ET2009M, ET3004M ET-M Series Gate Arrays DESCRIPTION The Fujitsu ET-M Series of ECL Gate Arrays are designed to provide both fast ECL
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d014b2bet2004met2009met3004m+5et-2009met-3004m149-leadcs31e4input nor gate
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74LS86 motorola
Abstract: 74LS86 full adder motorola 74LS86 74HG74 TTL 74ls83 74ls74 ALL 74LS74 motorola 74LS74 TTL 74ls74 MCA1200ECL
Contextual Info: LOGIC PRODUCTS — SEMICUSTOM continued Motorola Macrocell Array Families ft/i/t/t/t/t/t/à i / l / j / i / 1 / f/f /i Technology TTL ECL ECL/TTL 3-Mlcron Sllicon-Gate HCMOS 2-IMicron Sllicon-Gate HCMOS G ate E qu iva le nt 652 1192 2472 533 1280 2720 2958
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74ls83mc1018074hc28374ls86 motorola+974ls86 full addermotorola 74ls8674hg74ttl 74ls8374ls74all 74ls74motorola 74ls74ttl 74ls74mca1200ecl
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LH202
Abstract: LH293 motorola mca nor gate using TTL transistor I400 I403 LH201 h54 motorola mpa1
Contextual Info: Ami 850 Mixed ECL/TTL I/O Mask-Programmable Gate Array PRELIMINARY > 3 DISTINCTIVE CHARACTERISTICS Up to 1800 equivalent gates - 72 internal cells - Up to 80 l/O s H igh-perform ance, low -pow er ECL internal gates - W orst case T pd = 1.2 ns oo cn Large m acrocell library containing over 150 functions
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7429aca20687287alh202+9lh293motorola mcanor gate using ttltransistori400i403lh201h54 motorolampa1
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LBD8
Abstract: lt08 LT016
Contextual Info: ADV KICRO PLA /P LE /A R R A YS 13E D 1 05S7Sat. Q O a flà lt *1 I Am3530 Mixed ECL/TTL I/O Mask-Programmable Gate Array > 3 DISTINCTIVE CHARACTERISTICS GO 01 Integrated up to 410 ECL-equivalent gates in a 24-pin slim DIP , to eliminate "g lu e " logic, resulting in reduced
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05s7satam353024-pinalb-wcp-15m-9/88+3lbd8lt08lt016
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carry look ahead adder
Abstract: Q20010 Q20120 Q20000
Contextual Info: DEVICE SPECIFICATION LOGIC A R R A Y S 020000 Q20000 FEATURES T U R B O ” ECL/TTL Figure 6. Q20080 Die • • • • • • • • • • Up to 18,777 gates, channelless architecture 100 ps equivalent gate delays Low power 0.5-1.0 mW/gate 10K, 10KH, 100KECL and mixed ECL/TTL capability
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q20080q20000100keclq20004+5q20010q20025q20045q20120carry look ahead adder
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ECL2515
Abstract: ECL2500 ECL2516
Contextual Info: TYPES ECL2515, ECL2516 EMITTER-COUPLED-LOGIC ARITHMETIC MODULES ECL INTEGRATED CIRCUITS 09 H C -< ECL2500 SERIES E M ITT E R -C O U P LE D -LO G IC ECL A R IT H M E T IC M O D U LES FOR A P P L IC A T IO N IN U LTR A -H IG H -SPEED D IG IT A L SYSTEMS r-o
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ecl2515ecl2516ecl2500 |
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ZX03
Abstract: L328 H331 transistor transistor h331 ZX-03 H375 L322 L817 MCA10000ECL LH5022
Contextual Info: Order this data sheet by MCA10000ECL/D MOTOROLA MCA10000ECL ^ SEMICONDUCTOR TECHNICAL DATA M C A 10000E C L M ACRO CELL ARRAY M C A 3 ECL S E R IE S The MCA10000ECL A rra y is a m e m b e r o f M o to ro la 's "T h ird G e n e ra tio n " MCA3 ECL series. M o to ro la 's MOSAIC III process
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mca10000ecl/dmca10000eclzx03l328+7h331 transistortransistor h331zx-03h375l322l817lh5022
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